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optest8f.asm
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optest8f.asm
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* Centurion Opcode Tester (80-FF) by ren14500. Public domain.
*
* Assemble with P.ASM, hit SELECT to get to LOS and enter the executable name.
*
* Each instruction (in each addressing mode if applicable) has an example
* snippet. The special instructions may not do anything sensible, so run at
* your own risk. The snippets do not necessarily show a meaningful normal way
* to use the instruction, though most attempt to. Some (especially the extended
* addressing modes in BIGNUM and MEMBLOCK) make almost no sense at all, like
* literal->literal, but the ISA allows it, and it is classic Centurion style
* with self-modifying code.
*
* Notation in comments uses * instead of () to dereference to avoid confusion
* with parentheses used for grouping. This notation is also somewhat used in
* the assembly for indirect addressing. So "*WORD3" means the value found at the
* address labeled "WORD3". "*B" means the value found at the address held in the
* B register. "*(B+3)" means the value found at three plus the address held in
* the B register. "**B" means the value found at the address found at the
* address held in the B register. And so on - there are a lot of modes.
*
* Note that the term "string" in any comments does not mean ASCII strings that
* are human readable unless noted. It generally means any array of bytes.
*
* The CPU6-only instructions are noted when you see "CPU5 illegal start" and
* "CPU5 illegal end". Removing the instructions between those pairs will allow
* assembly with P.ASM5 (or S.ASM on a CPU5). In some cases the "CPU5 illegal
* start" includes a "JMP/ TESTILL", in which case the lines between the start/
* end should be replaced with that instruction instead for proper operation.
* All of the support code before and after the instruction snippets is CPU5-
* compatible. Thus, it is not necessarily the best way to do the same
* functionality on a CPU6 and should not be used as such.
*
* You will generally need to read the test code and then review the output
* after running the test to see what is happening as the output is generally
* terse - usually just the flags, registers, and/or memory after the operation.
* Note that the display of the P register is missing for most tests because it
* takes extra work to capture it. Wherever its value is important, it is being
* printed properly. On CPU5 it is not possible to capture it without changing
* flags, so it is not done there at all. See PRINTREGS for details.
*
* Instruction count notes:
*
* 1. Encodings that differ only in arguments beyond the opcode itself are not
* counted as separate instructions. Most Centurion instructions are almost
* perfectly orthogonal, so any register can be used with them, so it does
* not make sense to count each one as a separate instruction.
* 2. Each addressing mode is counted as a separate instruction. This is in line
* with ARM.
* 3. A CPU6 extension that does not add an addressing mode does not count as a
* separate instruction. E.g., INRB added the ability to increment by 1-16
* instead of just by 1. That is a single functionality still.
* 4. Conversely, adding addressing modes does count as separate instructions.
* E.g., XFR added three addressing modes to the previous functionality of
* register-to-register transfers, so it counts as four instructions.
* 5. Encodings that the assembler will never generate are still counted as
* separate instructions. E.g., the indirect addressing mode with no offset
* will always be encoded using the implicit register opcode, which is
* shorter, instead of the indexed direct encoding.
* 6. Instruction encodings that assemble but do not actually work are noted in
* comments but are not counted.
*
* Start of source.
TITLE 'OPTEST8F'
ZOPTEST8F BEGIN X'0100'
*
* Definitions.
CR EQU X'8D' ; Carriage return.
CRLF EQU X'8D8A' ; Carriage return and line feed.
LFNULL EQU X'8A00' ; Line feed and null terminator.
*
* Entry point.
ENTRY LDX= 32*1024 ; 32KB -> X.
XFR X,S ; Set the stack pointer to 32KB.
JSR/ PRINTNULL ; Print the welcome screen.
DW CRLF,2
DC 'OPTEST CPU'
DB 0
JSR/ INITINT ; Initialize interrupts.
JSR/ CPUTYPE ; Determine the CPU type.
JSR/ PRINTNULL ; Print the rest of the string.
DC ' DETECTED'
DW CRLF
DB 0
JSR/ PRINTMENU ; Print the menu.
JSR/ GET2HEX ; Get the selection -> A.
SLA ; A <<= 1.
LDB= OPTESTS ; Test function table -> B.
AAB ; A + B -> B.
JSR+ *B ; Jump to the selected function.
JSR/ PRINTNULL ; Print the reset prompt.
DC 'PRESS ANY KEY TO RESET> '
DB 0
JSR/ GETONE ; Wait for the key press.
JMP ENTRY ; Restart fresh.
*
* Values for opcode test use.
WORD0 DW X'0102'
WORD1 DW X'0304'
WORD2 DW X'0506'
WORD3 DW X'0708'
WORD4 DW X'090A'
WORD5 DW X'0B0C'
WORD6 DW X'0D0E'
WORD7 DW X'0F10'
WORD8 DW X'1112'
WORD9 DW X'1314'
WORDA DW X'1516'
WORDB DW X'1718'
WORD3ADDR DW WORD3
WORD4ADDR DW WORD4
WORD5ADDR DW WORD5
WORD9ADDR DW WORD9
WORDAADDR DW WORDA
WORDBADDR DW WORDB
BYTE0 EQU WORD0
BYTE1 EQU WORD0+1
BYTE2 EQU WORD1
BYTE3 EQU WORD1+1
BYTE4 EQU WORD2
BYTE5 EQU WORD2+1
BYTE6 EQU WORD3
BYTE7 EQU WORD3+1
BYTE8 EQU WORD4
BYTE9 EQU WORD4+1
BYTEA EQU WORD5
BYTEB EQU WORD5+1
BYTE3ADDR DW BYTE3
BYTE4ADDR DW BYTE4
BYTE5ADDR DW BYTE5
BYTE9ADDR DW BYTE9
BYTEAADDR DW BYTEA
BYTEBADDR DW BYTEB
*
* Buffer for opcode test use.
TBUFF DB X'FF',16 ; Initialize to all bits set.
TBUFFADDR DW TBUFF
*
* Hex dump the first byte of the test buffer. Clobbers A and B.
HEXT1 LDAB TBUFF ; AL = first byte of TBUFF.
JSR/ HEXBYTE ; Print it.
JSR/ PRINTNULL ; Get to a newline.
DW CRLF
DB 0
RSR ; Return.
*
* Hex dump the first 2 bytes of the test buffer. Clobbers A and B.
HEXT2 LDA= TBUFF ; A = TBUFF.
LDB= 2/2 ; B = 1 word.
JMP/ HBCRLF ; Dump.
*
* Hex dump the first 16 bytes of the test buffer. Clobbers A and B.
HEXT16 LDA= TBUFF ; A = TBUFF.
LDB= 16/2 ; B = 8 words.
JMP/ HBCRLF ; Dump.
*
* Default interrupt handler that just ignores the interrupt.
RIDEF RI ; Return from interrupt.
DEFINT JMP RIDEF ; Jump to the return.
*
* Abort interrupt handler.
ILL5 EQU X'F7' ; MVL, illegal on CPU5 but not CPU6.
ILL56 EQU X'E7' ; Illegal on CPU5 and CPU6.
ABORTFLAG DB 0 ; Flag set if abort occurs.
L0FLAGS DB 0 ; Level 0 flags (VMFL) in high nibble.
AISETFLGS DB 0 ; Non-0: L0FLAGS->flags; 0: flags->L0FLAGS.
RIABORT RI ; Return from interrupt.
ABORTINT CLAB ; AL = 0.
INAB ; AL = 1.
STAB ABORTFLAG ; Set the aborted flag.
LDAB AISETFLGS ; AL = AISETFLGS
BZ ABORTGET ; If set not requested, done.
LDAB L0FLAGS ; AL = L0FLAGS.
STAB/ X'000C'+1 ; AL -> level 0 C register low byte high nibble.
CLAB ; AL = 0.
STAB AISETFLGS ; AL -> AISETFLGS
STAB ABORTFLAG ; Reset the aborted flag since we were setting.
JMP ABORTEND ; Done.
ABORTGET LDAB/ X'000C'+1 ; C register low byte -> AL.
STAB L0FLAGS ; AL -> L0FLAGS.
ABORTEND JMP RIABORT ; Jump to the return.
*
* Set the current CPU flags to the value in the upper nibble of AL. AL is set
* to the value at SFSAVE+1.
SETFLAGS STAB L0FLAGS ; AL -> flags storage.
LDAB= 1 ; AL = 1.
STAB AISETFLGS ; AL -> set flags flag.
SFSAVE LDAB= 0 ; Load AL with saved value.
DB ILL56 ; Abort.
RSR ; Return.
*
* Set the current CPU flags to 0.
SETFLAGS0 STAB SFSAVE+1 ; Save AL to be restored.
CLAB ; AL = 0.
JMP SETFLAGS ; Set the flags.
*
* CPU5 illegal start
* JMP here instead of JSR PRINTREGS to capture P properly.
PRINTREGP STK X,2 ; Push X to the stack as if JSR did.
STK P,2 ; Push P to the stack before it gets changed.
* CPU5 illegal end
*
* Print all registers. Note that P is clobbered by JSR so if printing P is
* desired, a JMP instead of JSR to this subroutine must be performed. Set the
* word at PRX to the desired return address and JMP to PRINTREGP and it will
* simulate you JSRing here instead, minus the P clobber.
PRINTREGS DB ILL56 ; Abort.
STA- S- ; Push A to the stack.
* CPU5 illegal start
LDA/ PRX ; *PRX -> A.
BZ PRV ; If P not required, go to print flags.
LDA+ S,2 ; Get the pushed P into A.
STA/ PRP ; Save it for later printing..
LDA+ S ; Get the pushed A into A.
STA+ S+,2 ; Move it over the pushed P and adjust stack ptr.
* CPU5 illegal end
PRV LDAB L0FLAGS ; AL = flags.
XFRB AL,AU ; AL -> AU.
JSR/ PRINTNULL
DC 'V:'
DB 0
SLA ; A <<= 1.
BL PRV1 ; Branch if V set.
LDAB= '0' ; AL = ASCII 0.
JSR/ PRINTONE ; Print it.
JMP PRM ; Jump to minus flag.
PRV1 LDAB= '1' ; AL = ASCII 1.
JSR/ PRINTONE ; Print it.
PRM JSR/ PRINTNULL
DC ' M:'
DB 0
SLA ; A <<= 1.
BL PRM1 ; Branch if M set.
LDAB= '0' ; AL = ASCII 0.
JSR/ PRINTONE ; Print it.
JMP PRF ; Jump to fault flag.
PRM1 LDAB= '1' ; AL = ASCII 1.
JSR/ PRINTONE ; Print it.
PRF JSR/ PRINTNULL
DC ' F:'
DB 0
SLA ; A <<= 1.
BL PRF1 ; Branch if F set.
LDAB= '0' ; AL = ASCII 0.
JSR/ PRINTONE ; Print it.
JMP PRL ; Jump to link flag.
PRF1 LDAB= '1' ; AL = ASCII 1.
JSR/ PRINTONE ; Print it.
PRL JSR/ PRINTNULL
DC ' L:'
DB 0
SLA ; A <<= 1.
BL PRL1 ; Branch if L set.
LDAB= '0' ; AL = ASCII 0.
JSR/ PRINTONE ; Print it.
JMP PRA ; Jump to A.
PRL1 LDAB= '1' ; AL = ASCII 1.
JSR/ PRINTONE ; Print it.
PRA JSR/ PRINTNULL
DC ' A:'
DB 0
LDA+ S ; Get A back from the stack.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' B:'
DB 0
XFR B,A ; B -> A.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' X:'
DB 0
LDA+ S,2 ; Parent X (JSR pushed, we pushed A) -> A.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' Y:'
DB 0
XFR Y,A ; Y -> A.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' Z:'
DB 0
XFR Z,A ; Z -> A.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' S:'
DB 0
XFR S,A ; S -> A.
INA ; Increment A twice for the JSR which pushed X
INA ; to the stack.
INA ; Increment A twice more since we pushed A at the
INA ; beginning. That gives the parent S.
JSR/ HEXWORD ; Print it.
JSR/ PRINTNULL
DC ' C:'
DB 0
XFR C,A ; C -> A.
JSR/ HEXWORD ; Print it.
* CPU5 illegal start
LDA PRX ; *PRX -> A.
BZ PRDONE ; Skip P if PRX not set.
JSR/ PRINTNULL
DC ' P:'
DB 0
LDA PRP ; Saved P -> A.
JSR/ HEXWORD ; Print it.
LDX PRX ; *PRX -> X. RSR will "return" there.
CLA ; A = 0.
STA PRX ; A -> *PRX.
* CPU5 illegal end
PRDONE JSR/ PRINTNULL ; End the line.
DW CRLF
DB 0
LDA+ S+ ; Pop A from the stack.
RSR ; Return.
* CPU5 illegal start
PRP DW 0 ; Saved P.
PRX DW 0 ; X to load for RSR or 0 for normal RSR.
* CPU5 illegal end
*
* Initialize interrupts. The default ISR is set for all levels other than the
* abort level.
INITINT STA- S- ; Push A to the stack.
STB- S- ; Push B to the stack.
STX- S- ; Push X to the stack.
XFR Y,A ; Y -> A.
STA- S- ; Push Y to the stack.
XFR Z,A ; Z -> A.
STA- S- ; Push Z to the stack.
CLA ; A = 0 (page map 0).
LDB= DEFINT ; B = address of default interrupt handler.
LDX= X'010C' ; X = one set of registers past the end.
XFR X,Y ; X -> Y.
LDX= X'001C' ; X = interrupt level 1 C register.
II1 STA+ X+ ; Store A to C register, move X to P register.
STB+ X ; Store B to P register.
XFR X,Z ; X -> Z.
LDX= 14 ; X = 14.
ADD Z,X ; Move X to next interrupt level C register.
XFR X,Z ; X -> Z.
SUB Y,Z ; Z = Y - Z.
BNZ II1 ; Loop if not equal.
LDA= ABORTINT ; A = address of abort interrupt handler.
STA/ X'00FE' ; A -> abort level P register.
LDA+ S+ ; Pop Z from the stack.
XAZ ; A -> Z.
LDA+ S+ ; Pop Y from the stack.
XAY ; A -> Y.
LDX+ S+ ; Pop X from the stack.
LDB+ S+ ; Pop B from the stack.
LDA+ S+ ; Pop A from the stack.
EI ; Enable interrupts.
RSR ; Return.
*
* Determine the CPU type. Attempts to use MVL to copy the ISCPU5 flag to itself
* by setting A = 0 (length 1), B = Y = ISCPU5. On CPU6 this will work and do
* nothing noticeable. On CPU5 it will trigger an abort interrupt.
ISCPU5 DB 0 ; Zero if CPU6, non-zero if CPU5.
CPUTYPE STA- S- ; Push A to the stack.
STB- S- ; Push B to the stack.
XFR Y,A ; Y -> A.
STA- S- ; Push Y to the stack.
CLA ; A = 0 (MVL length = 1).
STAB/ ABORTFLAG ; AL -> abort flag.
LDB= ISCPU5 ; B = address of flag (MVL from address).
XFR B,Y ; B -> Y (MVL to address).
DB ILL5 ; An illegal opcode for CPU5 (MVL).
LDAB/ ABORTFLAG ; Abort flag -> AL.
STAB ISCPU5 ; AL -> CPU5 flag.
LDBB= '6' ; ASCII 6 -> BL.
SUBB BL,AL ; BL - AL -> AL.
JSR/ PRINTONE ; Print the CPU type.
CTDONE LDA+ S+ ; Pop Y from the stack.
XAY ; A -> Y.
LDB+ S+ ; Pop B from the stack.
LDA+ S+ ; Pop A from the stack.
RSR ; Return.
*
* Print the null-terminated string at X to the CRT.
PRINTNULL STAB- S- ; Push AL to the stack.
STBB- S- ; Push BL to the stack.
XFRB YL,AL ; YL -> AL.
STAB- S- ; Push YL to the stack.
LDAB= B'10' ; Set mask to check for transmit buffer empty.
XAYB ; AL -> YL.
PNLOOP LDBB+ X+ ; Load the next byte.
BZ PNEND ; If 0, we are done.
PNWAIT LDAB/ X'F200' ; AL = MUX status byte.
ANDB YL,AL ; Check if transmit buffer empty.
BZ PNWAIT ; If not empty, loop.
STBB/ X'F201' ; Store the character to the MUX data.
JMP PNLOOP ; Go to the next character.
PNEND LDAB+ S+ ; Pop YL from the stack.
XAYB ; AL -> YL.
LDBB+ S+ ; Pop BL from the stack.
LDAB+ S+ ; Pop AL from the stack.
RSR ; Return.
*
* Print the buffer at A of word length B in hex. Clobbers A and B.
HEXBUFF STX- S- ; Push X to the stack.
XAX ; A -> X.
HBLOOP LDA+ X+ ; (X) -> A, ++X.
JSR HEXWORD ; Dump A in hex.
LDAB= ' ' ; AL = ASCII space.
JSR PRINTONE ; Print space.
DCR B ; --B.
BNZ HBLOOP ;
LDX+ S+ ; Pop X from the stack.
RSR ; Return.
*
* Print the buffer at A of word length B in hex followed by CRLF. Clobbers A
* and B.
HBCRLF JSR HEXBUFF ; Print the buffer.
HBCRLF2 JSR/ PRINTNULL ; Print the CRLF.
DW CRLF
DB 0
RSR ; Return.
*
* Print A in hex followed by CRLF.
HACRLF JSR HEXWORD ; Print the word.
JMP HBCRLF2 ; Print the CRLF and return.
*
* Print AL in hex followed by CRLF.
HALCRLF JSR HEXBYTE ; Print the byte.
JMP HBCRLF2 ; Print the CRLF and return.
*
* Print A in hex.
HEXWORD STA- S- ; Push A to the stack.
XFRB AU,AL ; AU -> AL.
JSR HEXBYTE ; Print upper byte.
LDA+ S+ ; Pop A from the stack.
JMP HEXBYTE ; Print lower byte.
*
* Print AL in hex.
HEXBYTE STA- S- ; Push A to the stack.
STBB- S- ; Push BL to the stack.
XABB ; AL -> BL.
CLA ; A = 0.
XFRB BL,AL ; BL -> AL.
SRA ,4 ; A >>= 4.
JSR HEXNIBBLE ; Print the highest nibble.
LDAB= X'0F' ; AL = mask for low nibble.
ANDB BL,AL ; BL & AL -> AL.
JSR HEXNIBBLE ; Print the lowest nibble.
LDBB+ S+ ; Pop BL from the stack.
LDA+ S+ ; Pop A from the stack.
RSR ; Return.
*
* Print AL in hex. It must be a value in the range [0,15]. Clobbers AL.
HEXNIBBLE STBB- S- ; Push BL to the stack.
LDBB= 9 ; BL = 9.
SABB ; AL - BL -> BL.
BGZ HNLETTER ; If greater than 9, branch to print a letter.
LDBB= '0' ; BL = ASCII 0.
JMP HNPRINT ; Jump to print.
HNLETTER LDAB= 'A'-1 ; AL = ASCII A minus 1.
HNPRINT ADDB BL,AL ; BL + AL -> AL.
JSR PRINTONE ; Print it.
LDBB+ S+ ; Pop BL from the stack.
RSR ; Return.
*
* Print the character in AL to the CRT.
PRINTONE STBB- S- ; Push BL to the stack.
XFRB YL,BL ; YL -> BL.
STBB- S- ; Push YL to the stack.
LDBB= B'10' ; Set mask to check for transmit buffer empty.
XFRB BL,YL ; BL -> YL.
POWAIT LDBB/ X'F200' ; BL = MUX status byte.
ANDB YL,BL ; Check if transmit buffer empty.
BZ POWAIT ; If not empty, loop.
STAB/ X'F201' ; Store the character to the MUX data.
LDBB+ S+ ; Pop YL from the stack.
XFRB BL,YL ; BL -> YL.
LDBB+ S+ ; Pop BL from the stack.
RSR ; Return.
*
* Get a character from the CRT. Echo it and return it in AL.
GETONE STBB- S- ; Push BL to the stack.
GOWAIT LDBB/ X'F200' ; BL = MUX status byte.
SRRB BL ; BL = BL >> 1.
BNL GOWAIT ; If no character available, loop.
LDAB/ X'F201' ; AL = MUX data.
LDBB= X'80' ; BL = high bit set.
ORIB BL,AL ; AL = AL | BL.
JSR PRINTONE ; Echo the character.
LDBB+ S+ ; Pop BL from the stack.
RSR ; Return.
*
* Convert a hex character to integer value. The character is in AL and the value
* is returned in AL. AL is set to negative on error.
HEX2INT STB- S- ; Push B to the stack.
LDBB= '0' ; Load 0 to
SABB ; convert the ASCII to the value.
XFRB BL,BU ; BL -> BU.
BM H2IERROR ; If less than 0, error.
LDBB= ':' ; Load : to
SABB ; compare against decimal digits.
BM H2IEND ; If 0-9, done.
LDBB= 'A' ; Load A to
SABB ; convert the ASCII to a hex digit > 9.
XFRB BL,BU ; BL -> BU.
BM H2IERROR ; If less than 0, error.
LDBB= 'G' ; Load G to
SABB ; compare against hex digits A-F.
BP H2IERROR ; If G or more, error.
LDBB= 10 ; BL = 10.
ADDB BL,BU ; BL + BU -> BU.
JMP H2IEND ; Successful end.
H2IERROR LDB= -1 ; Signal an error.
H2IEND XFRB BU,AL ; BU -> AL.
LDB+ S+ ; Pop B from the stack.
RSR ; Return.
*
* Get a two-digit hex value, converted to integer, returned in A. Print a CRLF
* to get to a new line.
GET2HEX STBB- S- ; Push BL to the stack.
G2H0 JSR GETONE ; Get a character.
JSR HEX2INT ; Convert to integer.
XFRB AL,AL ; AL = AL.
BP G2H1 ; If no error, continue.
JSR/ PRINTNULL ; Print.
DW X'8788' ; Beep and (ADDS) backspace.
DB 0 ; Null terminator.
JMP G2H0 ; Get another character.
G2H1 SLAB ,4 ; AL <<= 4.
XFRB AL,BL ; AL -> BL.
G2H2 JSR GETONE ; Get a character.
JSR HEX2INT ; Convert to integer.
XFRB AL,AL ; AL = AL.
BP G2H3 ; If no error, continue.
JSR/ PRINTNULL ; Print.
DW X'8788' ; Beep and backspace.
DB 0 ; Null terminator.
JMP G2H2 ; Get another character.
G2H3 ORIB AL,BL ; AL | BL -> BL.
CLA ; A = 0.
XFRB BL,AL ; BL -> AL.
LDBB+ S+ ; Pop BL from the stack.
JSR/ PRINTNULL ; Print.
DW CRLF
DB 0
RSR ; Return.
*
* Prompt and wait for input to continue after printing AL blank lines. Clobbers
* AL.
MORE XFRB AL,AL ; AL -> AL.
BZ MPROMPT ; If zero, go to print the prompt.
JSR/ PRINTNULL ; Print a newline.
DW LFNULL ; LF, null terminator.
DCAB ; AL = AL - 1.
JMP MORE ; Loop.
MPROMPT JSR/ PRINTNULL ; Print a prompt.
DB CR ; CR only in case we are not at the beginning.
DC '(MORE)'
DB 0
JSR/ GETONE ; Wait for keypress.
LDAB= CR ; CR only to overwrite the prompt line.
JMP/ PRINTONE ; Print the CR.
*
* Print the main menu.
PRINTMENU JSR/ PRINTNULL ; Print menu items.
DC '80:LDAB= 81:LDAB/ 82:LDAB$ 83:LDAB 84:LDAB* 85:LDAB+/LDAB- 86:DPE(6)'
DW CRLF
DC '88:A 89:B 8A:X 8B:Y 8C:Z 8D:S 8E:C 8F:P'
DW CRLF
DC '90:LDA= 91:LDA/ 92:LDA$ 93:LDA 94:LDA* 95:LDA+/LDA- 96:SOP(6)'
DW CRLF
DC '98:A 99:B 9A:X 9B:Y 9C:Z 9D:S 9E:C 9F:P'
DW CRLF
DC 'A0:STAB= A1:STAB/ A2:STAB$ A3:STAB A4:STAB* A5:STAB+/STAB- A6:SEP(6)'
DW CRLF
DC 'A8:A A9:B AA:X AB:Y AC:Z AD:S AE:C AF:P'
DW CRLF
DC 'B0:STA= B1:STA/ B2:STA$ B3:STA B4:STA* B5:STA+/STA- B6:ECK(6)'
DW CRLF
DC 'B8:A B9:B BA:X BB:Y BC:Z BD:S BE:C BF:P'
DW CRLF
DC 'C0:LDBB= C1:LDBB/ C2:LDBB$ C3:LDBB C4:LDBB* C5:LDBB+/LDBB- C6:DCK(6)'
DW CRLF
DC 'C8:A C9:B CA:X CB:Y CC:Z CD:S CE:C CF:P'
DW CRLF
DC 'D0:LDB= D1:LDB/ D2:LDB$ D3:LDB D4:LDB* D5:LDB+/LDB- D6:STR(6) D7:SAR(6)'
DW CRLF
DC 'D8:A D9:B DA:X DB:Y DC:Z DD:S DE:C DF:P'
DW CRLF
DC 'E0:STBB= E1:STBB/ E2:STBB$ E3:STBB E4:STBB* E5:STBB+/STBB- E6:LAR(6)'
DW CRLF
DC 'E8:A E9:B EA:X EB:Y EC:Z ED:S EE:C EF:P'
DW CRLF
DC 'F0:STB= F1:STB/ F2:STB$ F3:STB F4:STB* F5:STB+/STB- F6:MMIO(6) F7:MVL(6) '
DC 'F8:A F9:B FA:X FB:Y FC:Z FD:S FE:C FF:P'
DW CRLF
DC 'ENTER SELECTION> '
DB 0
RSR ; Return.
*
* The table of opcode tests.
OPTESTS DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TESTILL
DW TEST80
DW TEST81
DW TEST82
DW TEST83
DW TEST84
DW TEST85
DW TEST86
DW TESTILL
DW TEST88
DW TEST89
DW TEST8A
DW TEST8B
DW TEST8C
DW TEST8D
DW TEST8E
DW TEST8F
DW TEST90
DW TEST91
DW TEST92
DW TEST93
DW TEST94
DW TEST95
DW TEST96
DW TESTILL
DW TEST98
DW TEST99
DW TEST9A
DW TEST9B
DW TEST9C
DW TEST9D
DW TEST9E
DW TEST9F
DW TESTA0
DW TESTA1
DW TESTA2
DW TESTA3
DW TESTA4
DW TESTA5
DW TESTA6
DW TESTILL
DW TESTA8
DW TESTA9
DW TESTAA
DW TESTAB
DW TESTAC
DW TESTAD
DW TESTAE
DW TESTAF
DW TESTB0
DW TESTB1
DW TESTB2
DW TESTB3
DW TESTB4
DW TESTB5
DW TESTB6
DW TESTILL
DW TESTB8
DW TESTB9
DW TESTBA
DW TESTBB
DW TESTBC
DW TESTBD
DW TESTBE
DW TESTBF
DW TESTC0
DW TESTC1
DW TESTC2
DW TESTC3
DW TESTC4
DW TESTC5
DW TESTC6
DW TESTILL
DW TESTC8
DW TESTC9
DW TESTCA
DW TESTCB
DW TESTCC
DW TESTCD
DW TESTCE
DW TESTCF
DW TESTD0
DW TESTD1
DW TESTD2
DW TESTD3
DW TESTD4
DW TESTD5
DW TESTD6
DW TESTD7
DW TESTD8
DW TESTD9
DW TESTDA
DW TESTDB
DW TESTDC
DW TESTDD
DW TESTDE
DW TESTDF
DW TESTE0
DW TESTE1
DW TESTE2
DW TESTE3
DW TESTE4
DW TESTE5
DW TESTE6
DW TESTILL
DW TESTE8
DW TESTE9
DW TESTEA
DW TESTEB
DW TESTEC
DW TESTED
DW TESTEE
DW TESTEF
DW TESTF0
DW TESTF1
DW TESTF2
DW TESTF3
DW TESTF4
DW TESTF5
DW TESTF6
DW TESTF7
DW TESTF8
DW TESTF9
DW TESTFA
DW TESTFB
DW TESTFC
DW TESTFD
DW TESTFE
DW TESTFF
*
* Illegal opcode function.
TESTILL JSR/ PRINTNULL
DC 'ILLEGAL OPCODE'
DW CRLF
DB 0
RSR ; Return.
*
* Test LDAB=.
* Load AL with the immediate byte argument. Flags are set according to the value
* loaded.
TEST80 JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 160
* CPU6 instruction # 924
T80 LDAB= -1 ; -1 -> AL.
* CPU5 instruction # 160
* CPU6 instruction # 924
JSR/ PRINTREGS ; Print the registers.
RSR ; Return.
*
* Test LDAB/.
* Load AL with the direct-addressed byte at the argument, which is a word
* address. Flags are set according to the value loaded.
TEST81 JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 161
* CPU6 instruction # 925
T81 LDAB/ BYTE0 ; *BYTE0 -> AL.
* CPU5 instruction # 161
* CPU6 instruction # 925
JSR/ PRINTREGS ; Print the registers.
RSR ; Return.
*
* Test LDAB$.
* Load AL with the indirect-addressed byte at the argument, which is a word
* address. Flags are set according to the value loaded.
TEST82 JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 162
* CPU6 instruction # 926
LDAB$ BYTE3ADDR ; **BYTE3ADDR -> AL.
* CPU5 instruction # 162
* CPU6 instruction # 926
JSR/ PRINTREGS ; Print the registers.
RSR ; Return.
*
* Test LDAB.
* Load AL with the relative-addressed byte at the argument, which is a signed
* byte displacement relative to the beginning of the next instruction. Flags
* are set according to the value loaded.
TEST83 JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 163
* CPU6 instruction # 927
LDAB T80+1 ; *(T80+1) -> AL.
* CPU5 instruction # 163
* CPU6 instruction # 927
JSR/ PRINTREGS ; Print the registers.
RSR ; Return.
*
* Test LDAB*.
* Load AL with the relative-indirect-addressed byte at the argument, which is a
* signed byte displacement relative to the beginning of the next instruction.
* Flags are set according to the value loaded.
TEST84 JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 164
* CPU6 instruction # 928
LDAB* T81+1 ; **(T81+1) -> AL.
* CPU5 instruction # 164
* CPU6 instruction # 928
JSR/ PRINTREGS ; Print the registers.
RSR ; Return.
*
* Test LDAB+/LDAB-.
* Load AL using an indexed-addressing mode. Either the + or - suffix is
* acceptable on the mnemonic - only the prefix and suffix on the index register
* affect the behavior. Any register can be used as the index register. There
* are twelve addressing modes possible:
* - (I) Indexed specifies the index register whose value is used as the address
* of the byte to load.
* - (IPI) Indexed post-incremented specifies the index register with a + suffix.
* The register is incremented by one after using it as the address of the
* byte to load.
* - (IPD) Indexed pre-decremented specifies the index register with a - suffix.
* The register is decremented by one before using it as the address of the
* byte to load.
* - (II) Indexed-indirect specifies the index register with a * prefix. The
* register value is used as an address at which is the word address of the
* byte to load.
* - (IIPI) Indexed-indirect post-incremented specifies the index register with
* a * prefix and + suffix. This loads the byte just as for indexed-indirect
* (II), then increments the register by two.
* - (IIPD) Indexed-indirect pre-decremented specifies the index register with a
* * prefix and - suffix. This decrements the register by two, then loads the
* byte just as for indexed-indirect (II).
* - (ID) Indexed-displaced specifies the index register followed by a comma and
* signed byte displacement. The register plus displacement is used as the
* address of the byte to load.
* - (IDPI) Indexed-displaced post-incremented specifies the register with a +
* suffix followed by a comma and signed byte displacement. This loads the
* byte just as for indexed-displaced (ID), then increments the register by
* one.
* - (IDPD) Indexed-displaced pre-decremented specifies the register with a
* - suffix followed by a comma and signed byte displacement. This decrements
* the register by one, then loads the byte just as for indexed-displaced (ID).
* - (IDI) Indexed-displaced-indirect specifies the index register with a
* * prefix followed by a comma and signed byte displacement. The register plus
* displacement is used as the address at which is the word address of the
* byte to load.
* - (IDIPI) Indexed-displaced-indirect post-incremented specifies the register
* with a * prefix and + suffix followed by a comma and signed byte
* displacement. This loads the byte just as for indexed-displaced-indirect
* (IDI), then increments the register by two.
* - (IDIPD) Indexed-displaced-indirect pre-decremented specifies the register
* with a * prefix and - suffix followed by a comma and signed byte
* displacement. This decrements the register by two, then loads the byte just
* as for indexed-displaced-indirect (IDI).
*
* The indexed (I) mode will always get encoded as one of the implicit register
* LDABs (88-8F) because those are shorter. The syntax is identical, but the
* encodings are completely different. The encoding is provided here. See the
* implicit register LDABs (88-8F) for actual syntax.
TEST85 LDB= BYTE0 ; B = BYTE0.
JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 165
* CPU6 instruction # 929
DW X'8520' ; *B -> AL (I). [alternate encoding of LDAB+ B]
* CPU5 instruction # 165
* CPU6 instruction # 929
JSR/ PRINTREGS ; Print the registers.
LDB= BYTE1 ; B = BYTE1.
JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 166
* CPU6 instruction # 930
LDAB+ B+ ; *B -> AL; B+1 -> B (IPI).
* CPU5 instruction # 166
* CPU6 instruction # 930
JSR/ PRINTREGS ; Print the registers.
LDB= BYTE2+1 ; B = one past BYTE2.
JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 167
* CPU6 instruction # 931
LDAB- B- ; B-1 -> B; *B -> AL (IPD).
* CPU5 instruction # 167
* CPU6 instruction # 931
JSR/ PRINTREGS ; Print the registers.
LDB= BYTE3ADDR ; B = BYTE3ADDR.
JSR/ SETFLAGS0 ; Reset flags.
* CPU5 instruction # 168
* CPU6 instruction # 932
LDAB+ *B ; **B -> AL (II).
* CPU5 instruction # 168