RISCV: Compressed Disasembly

[Sleigh-InSPECtor]

As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed a difference in the disassembly of various instructions in the compressed extension. The c.jr, c.addiw, c.lwsp, c.ldsp, c.lqsp all successfully decode when the rd register is zero, although this encoding is reserved for future use. To prevent this a nzcrd register has been added which excludes the zero register, and these instructions have been changed to use it.

The c.nop instruction encodes hardware hints when the immediate field is non-zero. Section 2.9 of the riscv-spec-20191213 describes hardware hints as ignore-able on hardware that does not support them as they do not change any architecturally visible state, except for advancing the pc. The current behaviour of c.nop excludes these from its encoding which causes them to fail to dissemble. The correct behaviour is to either include the hints into the encoding of the base instruction, or separate them out into a different hint instruction. As they have been included in the base instruction in other places the same has been done for the c.nop instruction.