AArch32: sha1su0.32 had a destructive 64-bit left shift on a 64-bit value before zext #6529
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* fixed destructive 64-bit left shift on a 64-bit value before zext
ryanmkurtz
added
Feature: Processor/ARM
Status: Triage
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As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed an unexpected behaviour in the
sha1su0.32instruction for both, AArch32 (ARM:LE:32:v8) & Thumb (ARM:LE:32:v8T).According to the manual, the expected behaviour is perform SHA1 schedule update 0 and store the value in the destination register. However, we noticed the output was incorrect.
e.g, for AArch32 with,
Instruction:
0xe00c70f2, sha1su0.32 q8,q8,q8initial_registers:
{ "q8": 0x8000000000000000 }We get:
Hardware:
{ "q8": 0x80000000000000000000000000000000 }Patched Spec:
{ "q8": 0x80000000000000000000000000000000 }Existing Spec:
{ "q8": 0x0 }e.g, for Thumb with,
Instruction:
0x70efe00c, sha1su0.32 q8,q8,q8initial_registers:
{ "q8": 0x8000000000000000 }We get:
Hardware:
{ "q8": 0x80000000000000000000000000000000 }Patched Spec:
{ "q8": 0x80000000000000000000000000000000 }Existing Spec:
{ "q8": 0x0 }Note: The patched spec does not introduce any disassembly changes to the best of our knowledge.