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mips.md
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mips.md
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;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989-2017 Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_enum "processor" [
r3000
4kc
4kp
5kc
5kf
20kc
24kc
24kf2_1
24kf1_1
74kc
74kf2_1
74kf1_1
74kf3_2
loongson_2e
loongson_2f
loongson_3a
m4k
octeon
octeon2
octeon3
r3900
r6000
r4000
r4100
r4111
r4120
r4130
r4300
r4600
r4650
r4700
r5000
r5400
r5500
r5900
r7000
r8000
r9000
r10000
sb1
sb1a
sr71000
xlr
xlp
p5600
m5100
i6400
])
(define_c_enum "unspec" [
;; Unaligned accesses.
UNSPEC_LOAD_LEFT
UNSPEC_LOAD_RIGHT
UNSPEC_STORE_LEFT
UNSPEC_STORE_RIGHT
;; Integer operations that are too cumbersome to describe directly.
UNSPEC_WSBH
UNSPEC_DSBH
UNSPEC_DSHD
;; Floating-point moves.
UNSPEC_LOAD_LOW
UNSPEC_LOAD_HIGH
UNSPEC_STORE_WORD
UNSPEC_MFHC1
UNSPEC_MTHC1
;; Floating-point environment.
UNSPEC_GET_FCSR
UNSPEC_SET_FCSR
;; HI/LO moves.
UNSPEC_MFHI
UNSPEC_MTHI
UNSPEC_SET_HILO
;; GP manipulation.
UNSPEC_LOADGP
UNSPEC_COPYGP
UNSPEC_MOVE_GP
UNSPEC_POTENTIAL_CPRESTORE
UNSPEC_CPRESTORE
UNSPEC_RESTORE_GP
UNSPEC_EH_RETURN
UNSPEC_GP
UNSPEC_SET_GOT_VERSION
UNSPEC_UPDATE_GOT_VERSION
;; Symbolic accesses.
UNSPEC_LOAD_CALL
UNSPEC_LOAD_GOT
UNSPEC_TLS_LDM
UNSPEC_TLS_GET_TP
UNSPEC_UNSHIFTED_HIGH
;; MIPS16 constant pools.
UNSPEC_ALIGN
UNSPEC_CONSTTABLE
UNSPEC_CONSTTABLE_END
UNSPEC_CONSTTABLE_INT
UNSPEC_CONSTTABLE_FLOAT
;; Blockage and synchronisation.
UNSPEC_BLOCKAGE
UNSPEC_CLEAR_HAZARD
UNSPEC_RDHWR
UNSPEC_SYNCI
UNSPEC_SYNC
;; Cache manipulation.
UNSPEC_MIPS_CACHE
UNSPEC_R10K_CACHE_BARRIER
;; Interrupt handling.
UNSPEC_ERET
UNSPEC_DERET
UNSPEC_DI
UNSPEC_EHB
UNSPEC_RDPGPR
UNSPEC_COP0
;; Used in a call expression in place of args_size. It's present for PIC
;; indirect calls where it contains args_size and the function symbol.
UNSPEC_CALL_ATTR
;; MIPS16 casesi jump table dispatch.
UNSPEC_CASESI_DISPATCH
;; Stack checking.
UNSPEC_PROBE_STACK_RANGE
;; The `.insn' pseudo-op.
UNSPEC_INSN_PSEUDO
])
(define_constants
[(TLS_GET_TP_REGNUM 3)
(GET_FCSR_REGNUM 2)
(SET_FCSR_REGNUM 4)
(MIPS16_T_REGNUM 24)
(PIC_FUNCTION_ADDR_REGNUM 25)
(RETURN_ADDR_REGNUM 31)
(CPRESTORE_SLOT_REGNUM 76)
(GOT_VERSION_REGNUM 79)
;; PIC long branch sequences are never longer than 100 bytes.
(MAX_PIC_BRANCH_LENGTH 100)
]
)
(include "predicates.md")
(include "constraints.md")
;; ....................
;;
;; Attributes
;;
;; ....................
(define_attr "got" "unset,xgot_high,load"
(const_string "unset"))
;; For jal instructions, this attribute is DIRECT when the target address
;; is symbolic and INDIRECT when it is a register.
(define_attr "jal" "unset,direct,indirect"
(const_string "unset"))
;; This attribute is YES if the instruction is a jal macro (not a
;; real jal instruction).
;;
;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
;; an instruction to restore $gp. Direct jals are also macros for
;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
;; into a register.
(define_attr "jal_macro" "no,yes"
(cond [(eq_attr "jal" "direct")
(symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
? JAL_MACRO_YES : JAL_MACRO_NO)")
(eq_attr "jal" "indirect")
(symbol_ref "(TARGET_CALL_CLOBBERED_GP
? JAL_MACRO_YES : JAL_MACRO_NO)")]
(const_string "no")))
;; Classification of moves, extensions and truncations. Most values
;; are as for "type" (see below) but there are also the following
;; move-specific values:
;;
;; constN move an N-constraint integer into a MIPS16 register
;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
;; to produce a sign-extended DEST, even if SRC is not
;; properly sign-extended
;; ext_ins EXT, DEXT, INS or DINS instruction
;; andi a single ANDI instruction
;; loadpool move a constant into a MIPS16 register by loading it
;; from the pool
;; shift_shift a shift left followed by a shift right
;;
;; This attribute is used to determine the instruction's length and
;; scheduling type. For doubleword moves, the attribute always describes
;; the split instructions; in some cases, it is more appropriate for the
;; scheduling type to be "multi" instead.
(define_attr "move_type"
"unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
shift_shift"
(const_string "unknown"))
(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor,simd_add"
(const_string "unknown"))
;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW,
V2DI,V4SI,V8HI,V16QI,V2DF,V4SF"
(const_string "unknown"))
;; True if the main data type is twice the size of a word.
(define_attr "dword_mode" "no,yes"
(cond [(and (eq_attr "mode" "DI,DF")
(not (match_test "TARGET_64BIT")))
(const_string "yes")
(and (eq_attr "mode" "TI,TF")
(match_test "TARGET_64BIT"))
(const_string "yes")]
(const_string "no")))
;; True if the main data type is four times of the size of a word.
(define_attr "qword_mode" "no,yes"
(cond [(and (eq_attr "mode" "TI,TF")
(not (match_test "TARGET_64BIT")))
(const_string "yes")]
(const_string "no")))
;; Attributes describing a sync loop. These loops have the form:
;;
;; if (RELEASE_BARRIER == YES) sync
;; 1: OLDVAL = *MEM
;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
;; CMP = 0 [delay slot]
;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
;; $AT |= $TMP1 | $TMP3
;; if (!commit (*MEM = $AT)) goto 1.
;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
;; CMP = 1
;; if (ACQUIRE_BARRIER == YES) sync
;; 2:
;;
;; where "$" values are temporaries and where the other values are
;; specified by the attributes below. Values are specified as operand
;; numbers and insns are specified as enums. If no operand number is
;; specified, the following values are used instead:
;;
;; - OLDVAL: $AT
;; - CMP: NONE
;; - NEWVAL: $AT
;; - INCLUSIVE_MASK: -1
;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
;; - EXCLUSIVE_MASK: 0
;;
;; MEM and INSN1_OP2 are required.
;;
;; Ideally, the operand attributes would be integers, with -1 meaning "none",
;; but the gen* programs don't yet support that.
(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
(const_string "move"))
(define_attr "sync_insn2" "nop,and,xor,not"
(const_string "nop"))
;; Memory model specifier.
;; "0"-"9" values specify the operand that stores the memory model value.
;; "10" specifies MEMMODEL_ACQ_REL,
;; "11" specifies MEMMODEL_ACQUIRE.
(define_attr "sync_memmodel" "" (const_int 10))
;; Accumulator operand for madd patterns.
(define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
;; call unconditional call
;; load load instruction(s)
;; fpload floating point load
;; fpidxload floating point indexed load
;; store store instruction(s)
;; fpstore floating point store
;; fpidxstore floating point indexed store
;; prefetch memory prefetch (register + offset)
;; prefetchx memory indexed prefetch (register + register)
;; condmove conditional moves
;; mtc transfer to coprocessor
;; mfc transfer from coprocessor
;; mthi transfer to a hi register
;; mtlo transfer to a lo register
;; mfhi transfer from a hi register
;; mflo transfer from a lo register
;; const load constant
;; arith integer arithmetic instructions
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
;; signext sign extend instructions
;; clz the clz and clo instructions
;; pop the pop instruction
;; trap trap if instructions
;; imul integer multiply 2 operands
;; imul3 integer multiply 3 operands
;; imul3nc integer multiply 3 operands without clobbering HI/LO
;; imadd integer multiply-add
;; idiv integer divide 2 operands
;; idiv3 integer divide 3 operands
;; move integer register move ({,D}ADD{,U} with rt = 0)
;; fmove floating point register move
;; fadd floating point add/subtract
;; fmul floating point multiply
;; fmadd floating point multiply-add
;; fdiv floating point divide
;; frdiv floating point reciprocal divide
;; frdiv1 floating point reciprocal divide step 1
;; frdiv2 floating point reciprocal divide step 2
;; fabs floating point absolute value
;; fneg floating point negation
;; fcmp floating point compare
;; fcvt floating point convert
;; fsqrt floating point square root
;; frsqrt floating point reciprocal square root
;; frsqrt1 floating point reciprocal square root step1
;; frsqrt2 floating point reciprocal square root step2
;; dspmac DSP MAC instructions not saturating the accumulator
;; dspmacsat DSP MAC instructions that saturate the accumulator
;; accext DSP accumulator extract instructions
;; accmod DSP accumulator modify instructions
;; dspalu DSP ALU instructions not saturating the result
;; dspalusat DSP ALU instructions that saturate the result
;; multi multiword sequence (or user asm statements)
;; atomic atomic memory update instruction
;; syncloop memory atomic operation implemented as a sync loop
;; nop no operation
;; ghost an instruction that produces no real code
;; multimem microMIPS multiword load and store
(define_attr "type"
"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
multi,atomic,syncloop,nop,ghost,multimem,
simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,
simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,
simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,
simd_permute,simd_shf,simd_sat,simd_pcnt,simd_copy,simd_branch,simd_cmsa,
simd_fminmax,simd_logic,simd_move,simd_load,simd_store"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")
(eq_attr "alu_type" "add,sub") (const_string "arith")
(eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
;; If a doubleword move uses these expensive instructions,
;; it is usually better to schedule them in the same way
;; as the singleword form, rather than as "multi".
(eq_attr "move_type" "load") (const_string "load")
(eq_attr "move_type" "fpload") (const_string "fpload")
(eq_attr "move_type" "store") (const_string "store")
(eq_attr "move_type" "fpstore") (const_string "fpstore")
(eq_attr "move_type" "mtc") (const_string "mtc")
(eq_attr "move_type" "mfc") (const_string "mfc")
(eq_attr "move_type" "mtlo") (const_string "mtlo")
(eq_attr "move_type" "mflo") (const_string "mflo")
;; These types of move are always single insns.
(eq_attr "move_type" "imul") (const_string "imul")
(eq_attr "move_type" "fmove") (const_string "fmove")
(eq_attr "move_type" "loadpool") (const_string "load")
(eq_attr "move_type" "signext") (const_string "signext")
(eq_attr "move_type" "ext_ins") (const_string "arith")
(eq_attr "move_type" "arith") (const_string "arith")
(eq_attr "move_type" "logical") (const_string "logical")
(eq_attr "move_type" "sll0") (const_string "shift")
(eq_attr "move_type" "andi") (const_string "logical")
;; These types of move are always split.
(eq_attr "move_type" "constN,shift_shift")
(const_string "multi")
;; These types of move are split for quadword modes only.
(and (eq_attr "move_type" "move,const")
(eq_attr "qword_mode" "yes"))
(const_string "multi")
;; These types of move are split for doubleword modes only.
(and (eq_attr "move_type" "move,const")
(eq_attr "dword_mode" "yes"))
(const_string "multi")
(eq_attr "move_type" "move") (const_string "move")
(eq_attr "move_type" "const") (const_string "const")
(eq_attr "sync_mem" "!none") (const_string "syncloop")]
(const_string "unknown")))
(define_attr "compact_form" "always,maybe,never"
(cond [(eq_attr "jal" "direct")
(const_string "always")
(eq_attr "jal" "indirect")
(const_string "maybe")
(eq_attr "type" "jump")
(const_string "maybe")]
(const_string "never")))
;; Mode for conversion types (fcvt)
;; I2S integer to float single (SI/DI to SF)
;; I2D integer to float double (SI/DI to DF)
;; S2I float to integer (SF to SI/DI)
;; D2I float to integer (DF to SI/DI)
;; D2S double to float single
;; S2D float single to double
(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
(const_string "unknown"))
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(if_then_else (ior ;; In general, constant-pool loads are extended
;; instructions. We don't yet optimize for 16-bit
;; PC-relative references.
(eq_attr "move_type" "sll0,loadpool")
(eq_attr "jal" "direct")
(eq_attr "got" "load"))
(const_string "yes")
(const_string "no")))
(define_attr "compression" "none,all,micromips32,micromips"
(const_string "none"))
(define_attr "enabled" "no,yes"
(cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between
;; GR_REG and FR_REG for 64-bit values.
(and (eq_attr "move_type" "mtc,mfc")
(match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1)
|| TARGET_O32_FP64A_ABI")
(eq_attr "dword_mode" "yes"))
(const_string "no")
(and (eq_attr "compression" "micromips32,micromips")
(match_test "!TARGET_MICROMIPS"))
(const_string "no")]
(const_string "yes")))
;; The number of individual instructions that a non-branch pattern generates,
;; using units of BASE_INSN_LENGTH.
(define_attr "insn_count" ""
(cond [;; "Ghost" instructions occupy no space.
(eq_attr "type" "ghost")
(const_int 0)
;; Extended instructions count as 2.
(and (eq_attr "extended_mips16" "yes")
(match_test "TARGET_MIPS16"))
(const_int 2)
;; A GOT load followed by an add of $gp. This is not used for MIPS16.
(eq_attr "got" "xgot_high")
(const_int 2)
;; SHIFT_SHIFTs are decomposed into two separate instructions.
;; They are extended instructions on MIPS16 targets.
(eq_attr "move_type" "shift_shift")
(if_then_else (match_test "TARGET_MIPS16")
(const_int 4)
(const_int 2))
;; Check for doubleword moves that are decomposed into two
;; instructions. The individual instructions are unextended
;; MIPS16 ones.
(and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
(eq_attr "dword_mode" "yes"))
(const_int 2)
;; Check for quadword moves that are decomposed into four
;; instructions.
(and (eq_attr "move_type" "mtc,mfc,move")
(eq_attr "qword_mode" "yes"))
(const_int 4)
;; Constants, loads and stores are handled by external routines.
(and (eq_attr "move_type" "const,constN")
(eq_attr "dword_mode" "yes"))
(symbol_ref "mips_split_const_insns (operands[1])")
(eq_attr "move_type" "const,constN")
(symbol_ref "mips_const_insns (operands[1])")
(eq_attr "move_type" "load,fpload")
(symbol_ref "mips_load_store_insns (operands[1], insn)")
(eq_attr "move_type" "store,fpstore")
(symbol_ref "mips_load_store_insns (operands[0], insn)
+ (TARGET_FIX_24K ? 1 : 0)")
;; In the worst case, a call macro will take 8 instructions:
;;
;; lui $25,%call_hi(FOO)
;; addu $25,$25,$28
;; lw $25,%call_lo(FOO)($25)
;; nop
;; jalr $25
;; nop
;; lw $gp,X($sp)
;; nop
(eq_attr "jal_macro" "yes")
(const_int 8)
;; Various VR4120 errata require a nop to be inserted after a macc
;; instruction. The assembler does this for us, so account for
;; the worst-case length here.
(and (eq_attr "type" "imadd")
(match_test "TARGET_FIX_VR4120"))
(const_int 2)
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
(and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")
(match_test "TARGET_FIX_VR4120"))
(const_int 2)
(eq_attr "type" "idiv,idiv3")
(symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))")
(not (eq_attr "sync_mem" "none"))
(symbol_ref "mips_sync_loop_insns (insn, operands)")]
(const_int 1)))
;; Length of instruction in bytes. The default is derived from "insn_count",
;; but there are special cases for branches (which must be handled here)
;; and for compressed single instructions.
(define_attr "length" ""
(cond [(and (ior (eq_attr "compression" "micromips,all")
(and (eq_attr "compression" "micromips32")
(eq_attr "mode" "SI,SF")))
(eq_attr "dword_mode" "no")
(match_test "TARGET_MICROMIPS"))
(const_int 2)
;; Direct microMIPS branch instructions have a range of
;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
;; If a branch is outside this range, we have a choice of two
;; sequences.
;;
;; For PIC, an out-of-range branch like:
;;
;; bne r1,r2,target
;; dslot
;;
;; becomes the equivalent of:
;;
;; beq r1,r2,1f
;; dslot
;; la $at,target
;; jr $at
;; nop
;; 1:
;;
;; The non-PIC case is similar except that we use a direct
;; jump instead of an la/jr pair. Since the target of this
;; jump is an absolute 28-bit bit address (the other bits
;; coming from the address of the delay slot) this form cannot
;; cross a 256MB boundary. We could provide the option of
;; using la/jr in this case too, but we do not do so at
;; present.
;;
;; The value we specify here does not account for the delay slot
;; instruction, whose length is added separately. If the RTL
;; pattern has no explicit delay slot, mips_adjust_insn_length
;; will add the length of the implicit nop. The range of
;; [-0x20000, 0x1fffc] from the address of the delay slot
;; therefore translates to a range of:
;;
;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
;; == [-0x1fffc, 0x1fff8]
;;
;; from the shorten_branches reference address.
(and (eq_attr "type" "branch")
(not (match_test "TARGET_MIPS16")))
(cond [;; Any variant can handle the 17-bit range.
(and (le (minus (match_dup 0) (pc)) (const_int 65532))
(le (minus (pc) (match_dup 0)) (const_int 65534)))
(const_int 4)
;; The 18-bit range is OK other than for microMIPS.
(and (not (match_test "TARGET_MICROMIPS"))
(and (le (minus (match_dup 0) (pc)) (const_int 131064))
(le (minus (pc) (match_dup 0)) (const_int 131068))))
(const_int 4)
;; The non-PIC case: branch, first delay slot, and J.
(match_test "TARGET_ABSOLUTE_JUMPS")
(const_int 12)]
;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
;; mips_adjust_insn_length substitutes the correct length.
;;
;; Note that we can't simply use (symbol_ref ...) here
;; because genattrtab needs to know the maximum length
;; of an insn.
(const_int MAX_PIC_BRANCH_LENGTH))
;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
;; from the address of the following instruction, which leads
;; to a range of:
;;
;; [-(0x100 - sizeof (branch)), 0xfe]
;; == [-0xfe, 0xfe]
;;
;; from the shorten_branches reference address. Extended branches
;; likewise have a range of [-0x10000, 0xfffe] from the address
;; of the following instruction, which leads to a range of:
;;
;; [-(0x10000 - sizeof (branch)), 0xfffe]
;; == [-0xfffc, 0xfffe]
;;
;; from the reference address.
;;
;; When a branch is out of range, mips_reorg splits it into a form
;; that uses in-range branches. There are four basic sequences:
;;
;; (1) Absolute addressing with a readable text segment
;; (32-bit addresses):
;;
;; b... foo 2 bytes
;; move $1,$2 2 bytes
;; lw $2,label 2 bytes
;; jr $2 2 bytes
;; move $2,$1 2 bytes
;; .align 2 0 or 2 bytes
;; label:
;; .word target 4 bytes
;; foo:
;; (16 bytes in the worst case)
;;
;; (2) Absolute addressing with a readable text segment
;; (64-bit addresses):
;;
;; b... foo 2 bytes
;; move $1,$2 2 bytes
;; ld $2,label 2 bytes
;; jr $2 2 bytes
;; move $2,$1 2 bytes
;; .align 3 0 to 6 bytes
;; label:
;; .dword target 8 bytes
;; foo:
;; (24 bytes in the worst case)
;;
;; (3) Absolute addressing without a readable text segment
;; (which requires 32-bit addresses at present):
;;
;; b... foo 2 bytes
;; move $1,$2 2 bytes
;; lui $2,%hi(target) 4 bytes
;; sll $2,8 2 bytes
;; sll $2,8 2 bytes
;; addiu $2,%lo(target) 4 bytes
;; jr $2 2 bytes
;; move $2,$1 2 bytes
;; foo:
;; (20 bytes)
;;
;; (4) PIC addressing (which requires 32-bit addresses at present):
;;
;; b... foo 2 bytes
;; move $1,$2 2 bytes
;; lw $2,cprestore 0, 2 or 4 bytes
;; lw $2,%got(target)($2) 4 bytes
;; addiu $2,%lo(target) 4 bytes
;; jr $2 2 bytes
;; move $2,$1 2 bytes
;; foo:
;; (20 bytes in the worst case)
(and (eq_attr "type" "branch")
(match_test "TARGET_MIPS16"))
(cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
(le (minus (pc) (match_dup 0)) (const_int 254)))
(const_int 2)
(and (le (minus (match_dup 0) (pc)) (const_int 65534))
(le (minus (pc) (match_dup 0)) (const_int 65532)))
(const_int 4)
(and (match_test "TARGET_ABICALLS")
(not (match_test "TARGET_ABSOLUTE_ABICALLS")))
(const_int 20)
(match_test "Pmode == SImode")
(const_int 16)
] (const_int 24))]
(symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH")))
;; Attribute describing the processor.
(define_enum_attr "cpu" "processor"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
;; DELAY means that the next instruction cannot read the result
;; of this one. HILO means that the next two instructions cannot
;; write to HI or LO.
(define_attr "hazard" "none,delay,hilo,forbidden_slot"
(cond [(and (eq_attr "type" "load,fpload,fpidxload")
(match_test "ISA_HAS_LOAD_DELAY"))
(const_string "delay")
(and (eq_attr "type" "mfc,mtc")
(match_test "ISA_HAS_XFER_DELAY"))
(const_string "delay")
(and (eq_attr "type" "fcmp")
(match_test "ISA_HAS_FCMP_DELAY"))
(const_string "delay")
;; The r4000 multiplication patterns include an mflo instruction.
(and (eq_attr "type" "imul")
(match_test "TARGET_FIX_R4000"))
(const_string "hilo")
(and (eq_attr "type" "mfhi,mflo")
(not (match_test "ISA_HAS_HILO_INTERLOCKS")))
(const_string "hilo")]
(const_string "none")))
;; Can the instruction be put into a delay slot?
(define_attr "can_delay" "no,yes"
(if_then_else (and (eq_attr "type" "!branch,call,jump")
(eq_attr "hazard" "none")
(match_test "get_attr_insn_count (insn) == 1"))
(const_string "yes")
(const_string "no")))
;; Attribute defining whether or not we can use the branch-likely
;; instructions.
(define_attr "branch_likely" "no,yes"
(if_then_else (match_test "GENERATE_BRANCHLIKELY")
(const_string "yes")
(const_string "no")))
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
(if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
(const_string "yes")
(const_string "no")))
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "type" "multi")
(set_attr "can_delay" "no")])
;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
;; from the same template.
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
;; A copy of GPR that can be used when a pattern has two independent
;; modes.
(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
(define_mode_iterator MOVEP1 [SI SF])
(define_mode_iterator MOVEP2 [SI SF])
(define_mode_iterator JOIN_MODE [HI
SI
(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT")])
;; This mode iterator allows :HILO to be used as the mode of the
;; concatenated HI and LO registers.
(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
(CC "TARGET_HARD_FLOAT
&& !TARGET_LOONGSON_2EF
&& !TARGET_MIPS5900")])
;; This mode iterator allows :FPCC to be used anywhere that an FP condition
;; is needed.
(define_mode_iterator FPCC [(CC "!ISA_HAS_CCF")
(CCF "ISA_HAS_CCF")])
;; 32-bit integer moves for which we provide move patterns.
(define_mode_iterator IMOVE32
[SI
(V2HI "TARGET_DSP")
(V4QI "TARGET_DSP")
(V2HQ "TARGET_DSP")
(V2UHQ "TARGET_DSP")
(V2HA "TARGET_DSP")
(V2UHA "TARGET_DSP")
(V4QQ "TARGET_DSP")
(V4UQQ "TARGET_DSP")])
;; 64-bit modes for which we provide move patterns.
(define_mode_iterator MOVE64
[DI DF
(V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
(V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
;; 128-bit modes for which we provide move patterns on 64-bit targets.
(define_mode_iterator MOVE128 [TI TF])
;; This mode iterator allows the QI and HI extension patterns to be
;; defined from the same template.
(define_mode_iterator SHORT [QI HI])
;; Likewise the 64-bit truncate-and-shift patterns.
(define_mode_iterator SUBDI [QI HI SI])
;; This mode iterator allows :ANYF to be used wherever a scalar or vector
;; floating-point mode is allowed.
(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
(V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
;; Like ANYF, but only applies to scalar modes.
(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
;; A floating-point mode for which moves involving FPRs may need to be split.
(define_mode_iterator SPLITF
[(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
(V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
(TF "TARGET_64BIT && TARGET_FLOAT64")])
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")
(QQ "") (HQ "") (SQ "") (DQ "d")
(UQQ "") (UHQ "") (USQ "") (UDQ "d")
(HA "") (SA "") (DA "d")
(UHA "") (USA "") (UDA "d")])
;; Same as d but upper-case.
(define_mode_attr D [(SI "") (DI "D")
(QQ "") (HQ "") (SQ "") (DQ "D")
(UQQ "") (UHQ "") (USQ "") (UDQ "D")
(HA "") (SA "") (DA "D")
(UHA "") (USA "") (UDA "D")])
;; This attribute gives the length suffix for a load or store instruction.
;; The same suffixes work for zero and sign extensions.
(define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
(define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
;; This attributes gives the mode mask of a SHORT.
(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
;; Mode attributes for GPR loads.
(define_mode_attr load [(SI "lw") (DI "ld")])
;; Instruction names for stores.
(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
;; Similarly for MIPS IV indexed FPR loads and stores.
(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
;; The unextended ranges of the MIPS16 addiu and daddiu instructions
;; are different. Some forms of unextended addiu have an 8-bit immediate
;; field but the equivalent daddiu has only a 5-bit field.
(define_mode_attr si8_di5 [(SI "8") (DI "5")])
;; This attribute gives the best constraint to use for registers of
;; a given mode.
(define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")])
;; This attribute gives the format suffix for floating-point operations.
(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
;; This attribute gives the upper-case mode name for one unit of a
;; floating-point mode or vector mode.
(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF") (V4SF "SF")
(V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI")
(V2DF "DF")])
;; This attribute gives the integer mode that has the same size as a
;; fixed-point mode.
(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
(UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
(HA "HI") (SA "SI") (DA "DI")
(UHA "HI") (USA "SI") (UDA "DI")
(V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
(V2HQ "SI") (V2HA "SI")])
;; This attribute gives the integer mode that has half the size of
;; the controlling mode.
(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
(V2SI "SI") (V4HI "SI") (V8QI "SI")
(TF "DI")])
;; This attribute works around the early SB-1 rev2 core "F2" erratum:
;;
;; In certain cases, div.s and div.ps may have a rounding error
;; and/or wrong inexact flag.
;;
;; Therefore, we only allow div.s if not working around SB-1 rev2
;; errata or if a slight loss of precision is OK.
(define_mode_attr divide_condition
[DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
(V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
;; This attribute gives the conditions under which SQRT.fmt instructions
;; can be used.
(define_mode_attr sqrt_condition
[(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
;; This attribute provides the correct mnemonic for each FP condition mode.
(define_mode_attr fpcmp [(CC "c") (CCF "cmp")])
;; This code iterator allows signed and unsigned widening multiplications
;; to use the same template.
(define_code_iterator any_extend [sign_extend zero_extend])
;; This code iterator allows the two right shift instructions to be
;; generated from the same template.
(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
;; This code iterator allows the three shift instructions to be generated
;; from the same template.
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
;; This code iterator allows unsigned and signed division to be generated
;; from the same template.
(define_code_iterator any_div [div udiv])
;; This code iterator allows unsigned and signed modulus to be generated
;; from the same template.
(define_code_iterator any_mod [mod umod])
;; This code iterator allows addition and subtraction to be generated
;; from the same template.
(define_code_iterator addsub [plus minus])
;; This code iterator allows all native floating-point comparisons to be
;; generated from the same template.
(define_code_iterator fcond [unordered uneq unlt unle eq lt le
(ordered "ISA_HAS_CCF")
(ltgt "ISA_HAS_CCF")
(ne "ISA_HAS_CCF")])
;; This code iterator is used for comparisons that can be implemented
;; by swapping the operands.
(define_code_iterator swapped_fcond [ge gt unge ungt])
;; Equality operators.
(define_code_iterator equality_op [eq ne])
;; These code iterators allow the signed and unsigned scc operations to use
;; the same template.
(define_code_iterator any_gt [gt gtu])
(define_code_iterator any_ge [ge geu])
(define_code_iterator any_lt [lt ltu])
(define_code_iterator any_le [le leu])
(define_code_iterator any_return [return simple_return])