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tc-mips.c
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tc-mips.c
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/* tc-mips.c -- assemble code for a MIPS chip.
Copyright (C) 1993-2022 Free Software Foundation, Inc.
Contributed by the OSF and Ralph Campbell.
Written by Keith Knowles and Ralph Campbell, working independently.
Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
Support.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "as.h"
#include "config.h"
#include "subsegs.h"
#include "safe-ctype.h"
#include "opcode/mips.h"
#include "itbl-ops.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"
/* Check assumptions made in this file. */
typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
#ifdef DEBUG
#define DBG(x) printf x
#else
#define DBG(x)
#endif
#define streq(a, b) (strcmp (a, b) == 0)
#define SKIP_SPACE_TABS(S) \
do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
/* Clean up namespace so we can include obj-elf.h too. */
static int mips_output_flavor (void);
static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
#undef OBJ_PROCESS_STAB
#undef OUTPUT_FLAVOR
#undef S_GET_ALIGN
#undef S_GET_SIZE
#undef S_SET_ALIGN
#undef S_SET_SIZE
#undef obj_frob_file
#undef obj_frob_file_after_relocs
#undef obj_frob_symbol
#undef obj_pop_insert
#undef obj_sec_sym_ok_for_reloc
#undef OBJ_COPY_SYMBOL_ATTRIBUTES
#include "obj-elf.h"
/* Fix any of them that we actually care about. */
#undef OUTPUT_FLAVOR
#define OUTPUT_FLAVOR mips_output_flavor()
#include "elf/mips.h"
#ifndef ECOFF_DEBUGGING
#define NO_ECOFF_DEBUGGING
#define ECOFF_DEBUGGING 0
#endif
int mips_flag_mdebug = -1;
/* Control generation of .pdr sections. Off by default on IRIX: the native
linker doesn't know about and discards them, but relocations against them
remain, leading to rld crashes. */
#ifdef TE_IRIX
int mips_flag_pdr = false;
#else
int mips_flag_pdr = true;
#endif
#include "ecoff.h"
static char *mips_regmask_frag;
static char *mips_flags_frag;
#define ZERO 0
#define ATREG 1
#define S0 16
#define S7 23
#define TREG 24
#define PIC_CALL_REG 25
#define KT0 26
#define KT1 27
#define GP 28
#define SP 29
#define FP 30
#define RA 31
#define FCSR 31
#define ILLEGAL_REG (32)
#define AT mips_opts.at
extern int target_big_endian;
/* The name of the readonly data section. */
#define RDATA_SECTION_NAME ".rodata"
/* Ways in which an instruction can be "appended" to the output. */
enum append_method {
/* Just add it normally. */
APPEND_ADD,
/* Add it normally and then add a nop. */
APPEND_ADD_WITH_NOP,
/* Turn an instruction with a delay slot into a "compact" version. */
APPEND_ADD_COMPACT,
/* Insert the instruction before the last one. */
APPEND_SWAP
};
/* Information about an instruction, including its format, operands
and fixups. */
struct mips_cl_insn
{
/* The opcode's entry in mips_opcodes or mips16_opcodes. */
const struct mips_opcode *insn_mo;
/* The 16-bit or 32-bit bitstring of the instruction itself. This is
a copy of INSN_MO->match with the operands filled in. If we have
decided to use an extended MIPS16 instruction, this includes the
extension. */
unsigned long insn_opcode;
/* The name if this is an label. */
char label[16];
/* The target label name if this is an branch. */
char target[16];
/* The frag that contains the instruction. */
struct frag *frag;
/* The offset into FRAG of the first instruction byte. */
long where;
/* The relocs associated with the instruction, if any. */
fixS *fixp[3];
/* True if this entry cannot be moved from its current position. */
unsigned int fixed_p : 1;
/* True if this instruction occurred in a .set noreorder block. */
unsigned int noreorder_p : 1;
/* True for mips16 instructions that jump to an absolute address. */
unsigned int mips16_absolute_jump_p : 1;
/* True if this instruction is complete. */
unsigned int complete_p : 1;
/* True if this instruction is cleared from history by unconditional
branch. */
unsigned int cleared_p : 1;
};
/* The ABI to use. */
enum mips_abi_level
{
NO_ABI = 0,
O32_ABI,
O64_ABI,
N32_ABI,
N64_ABI,
EABI_ABI
};
/* MIPS ABI we are using for this output file. */
static enum mips_abi_level mips_abi = NO_ABI;
/* Whether or not we have code that can call pic code. */
int mips_abicalls = false;
/* Whether or not we have code which can be put into a shared
library. */
static bool mips_in_shared = true;
/* This is the set of options which may be modified by the .set
pseudo-op. We use a struct so that .set push and .set pop are more
reliable. */
struct mips_set_options
{
/* MIPS ISA (Instruction Set Architecture) level. This is set to -1
if it has not been initialized. Changed by `.set mipsN', and the
-mipsN command line option, and the default CPU. */
int isa;
/* Enabled Application Specific Extensions (ASEs). Changed by `.set
<asename>', by command line options, and based on the default
architecture. */
int ase;
/* Whether we are assembling for the mips16 processor. 0 if we are
not, 1 if we are, and -1 if the value has not been initialized.
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
-nomips16 command line options, and the default CPU. */
int mips16;
/* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
1 if we are, and -1 if the value has not been initialized. Changed
by `.set micromips' and `.set nomicromips', and the -mmicromips
and -mno-micromips command line options, and the default CPU. */
int micromips;
/* Non-zero if we should not reorder instructions. Changed by `.set
reorder' and `.set noreorder'. */
int noreorder;
/* Non-zero if we should not permit the register designated "assembler
temporary" to be used in instructions. The value is the register
number, normally $at ($1). Changed by `.set at=REG', `.set noat'
(same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
unsigned int at;
/* Non-zero if we should warn when a macro instruction expands into
more than one machine instruction. Changed by `.set nomacro' and
`.set macro'. */
int warn_about_macros;
/* Non-zero if we should not move instructions. Changed by `.set
move', `.set volatile', `.set nomove', and `.set novolatile'. */
int nomove;
/* Non-zero if we should not optimize branches by moving the target
of the branch into the delay slot. Actually, we don't perform
this optimization anyhow. Changed by `.set bopt' and `.set
nobopt'. */
int nobopt;
/* Non-zero if we should not autoextend mips16 instructions.
Changed by `.set autoextend' and `.set noautoextend'. */
int noautoextend;
/* True if we should only emit 32-bit microMIPS instructions.
Changed by `.set insn32' and `.set noinsn32', and the -minsn32
and -mno-insn32 command line options. */
bool insn32;
/* Restrict general purpose registers and floating point registers
to 32 bit. This is initially determined when -mgp32 or -mfp32
is passed but can changed if the assembler code uses .set mipsN. */
int gp;
int fp;
/* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
command line option, and the default CPU. */
int arch;
/* True if ".set sym32" is in effect. */
bool sym32;
/* True if floating-point operations are not allowed. Changed by .set
softfloat or .set hardfloat, by command line options -msoft-float or
-mhard-float. The default is false. */
bool soft_float;
/* True if only single-precision floating-point operations are allowed.
Changed by .set singlefloat or .set doublefloat, command-line options
-msingle-float or -mdouble-float. The default is false. */
bool single_float;
/* 1 if single-precision operations on odd-numbered registers are
allowed. */
int oddspreg;
/* The set of ASEs that should be enabled for the user specified
architecture. This cannot be inferred from 'arch' for all cores
as processors only have a unique 'arch' if they add architecture
specific instructions (UDI). */
int init_ase;
};
/* Specifies whether module level options have been checked yet. */
static bool file_mips_opts_checked = false;
/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
value has not been initialized. Changed by `.nan legacy' and
`.nan 2008', and the -mnan=legacy and -mnan=2008 command line
options, and the default CPU. */
static int mips_nan2008 = -1;
/* This is the struct we use to hold the module level set of options.
Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
fp fields to -1 to indicate that they have not been initialized. */
static struct mips_set_options file_mips_opts =
{
/* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
/* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
/* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
/* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
/* init_ase */ 0
};
/* This is similar to file_mips_opts, but for the current set of options. */
static struct mips_set_options mips_opts =
{
/* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
/* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
/* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
/* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
/* init_ase */ 0
};
/* Which bits of file_ase were explicitly set or cleared by ASE options. */
static unsigned int file_ase_explicit;
/* These variables are filled in with the masks of registers used.
The object format code reads them and puts them in the appropriate
place. */
unsigned long mips_gprmask;
unsigned long mips_cprmask[4];
/* True if any MIPS16 code was produced. */
static int file_ase_mips16;
#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
|| mips_opts.isa == ISA_MIPS32R2 \
|| mips_opts.isa == ISA_MIPS32R3 \
|| mips_opts.isa == ISA_MIPS32R5 \
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.isa == ISA_MIPS64R3 \
|| mips_opts.isa == ISA_MIPS64R5)
/* True if any microMIPS code was produced. */
static int file_ase_micromips;
/* True if we want to create R_MIPS_JALR for jalr $25. */
#ifdef TE_IRIX
#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
#else
/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
because there's no place for any addend, the only acceptable
expression is a bare symbol. */
#define MIPS_JALR_HINT_P(EXPR) \
(!HAVE_IN_PLACE_ADDENDS \
|| ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
#endif
/* The argument of the -march= flag. The architecture we are assembling. */
static const char *mips_arch_string;
/* The argument of the -mtune= flag. The architecture for which we
are optimizing. */
static int mips_tune = CPU_UNKNOWN;
static const char *mips_tune_string;
/* True when generating 32-bit code for a 64-bit processor. */
static int mips_32bitmode = 0;
/* True if the given ABI requires 32-bit registers. */
#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
/* Likewise 64-bit registers. */
#define ABI_NEEDS_64BIT_REGS(ABI) \
((ABI) == N32_ABI \
|| (ABI) == N64_ABI \
|| (ABI) == O64_ABI)
#define ISA_IS_R6(ISA) \
((ISA) == ISA_MIPS32R6 \
|| (ISA) == ISA_MIPS64R6)
/* Return true if ISA supports 64 bit wide gp registers. */
#define ISA_HAS_64BIT_REGS(ISA) \
((ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS5 \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6)
/* Return true if ISA supports 64 bit wide float registers. */
#define ISA_HAS_64BIT_FPRS(ISA) \
((ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS5 \
|| (ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS32R3 \
|| (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS32R6 \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6)
/* Return true if ISA supports 64-bit right rotate (dror et al.)
instructions. */
#define ISA_HAS_DROR(ISA) \
((ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6 \
|| (mips_opts.micromips \
&& ISA_HAS_64BIT_REGS (ISA)) \
)
/* Return true if ISA supports 32-bit right rotate (ror et al.)
instructions. */
#define ISA_HAS_ROR(ISA) \
((ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS32R3 \
|| (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS32R6 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6 \
|| (mips_opts.ase & ASE_SMARTMIPS) \
|| mips_opts.micromips \
)
/* Return true if ISA supports single-precision floats in odd registers. */
#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
(((ISA) == ISA_MIPS32 \
|| (ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS32R3 \
|| (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS32R6 \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6 \
|| (CPU) == CPU_R5900) \
&& ((CPU) != CPU_GS464 \
|| (CPU) != CPU_GS464E \
|| (CPU) != CPU_GS264E))
/* Return true if ISA supports move to/from high part of a 64-bit
floating-point register. */
#define ISA_HAS_MXHC1(ISA) \
((ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS32R3 \
|| (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS32R6 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6)
/* Return true if ISA supports legacy NAN. */
#define ISA_HAS_LEGACY_NAN(ISA) \
((ISA) == ISA_MIPS1 \
|| (ISA) == ISA_MIPS2 \
|| (ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS5 \
|| (ISA) == ISA_MIPS32 \
|| (ISA) == ISA_MIPS32R2 \
|| (ISA) == ISA_MIPS32R3 \
|| (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2 \
|| (ISA) == ISA_MIPS64R3 \
|| (ISA) == ISA_MIPS64R5)
#define GPR_SIZE \
(mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
? 32 \
: mips_opts.gp)
#define FPR_SIZE \
(mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
? 32 \
: mips_opts.fp)
#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
/* True if relocations are stored in-place. */
#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
/* The ABI-derived address size. */
#define HAVE_64BIT_ADDRESSES \
(GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
/* The size of symbolic constants (i.e., expressions of the form
"SYMBOL" or "SYMBOL + OFFSET"). */
#define HAVE_32BIT_SYMBOLS \
(HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
/* Addresses are loaded in different ways, depending on the address size
in use. The n32 ABI Documentation also mandates the use of additions
with overflow checking, but existing implementations don't follow it. */
#define ADDRESS_ADD_INSN \
(HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
#define ADDRESS_ADDI_INSN \
(HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
#define ADDRESS_LOAD_INSN \
(HAVE_32BIT_ADDRESSES ? "lw" : "ld")
#define ADDRESS_STORE_INSN \
(HAVE_32BIT_ADDRESSES ? "sw" : "sd")
/* Return true if the given CPU supports the MIPS16 ASE. */
#define CPU_HAS_MIPS16(cpu) \
(startswith (TARGET_CPU, "mips16") \
|| startswith (TARGET_CANONICAL, "mips-lsi-elf"))
/* Return true if the given CPU supports the microMIPS ASE. */
#define CPU_HAS_MICROMIPS(cpu) 0
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
/* True if CPU has a ror instruction. */
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
/* True if CPU is in the Octeon family. */
#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
|| (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
/* True, if CPU has support for ldc1 and sdc1. */
#define CPU_HAS_LDC1_SDC1(CPU) \
((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
According to MIPS specifications, MIPS ISAs I, II, and III need
(at least) two instructions between the reads of HI/LO and
instructions which write them, and later ISAs do not. Contradicting
the MIPS specifications, some MIPS IV processor user manuals (e.g.
the UM for the NEC Vr5000) document needing the instructions between
HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
MIPS64 and later ISAs to have the interlocks, plus any specific
earlier-ISA CPUs for which CPU documentation declares that the
instructions are really interlocked. */
#define hilo_interlocks \
(mips_opts.isa == ISA_MIPS32 \
|| mips_opts.isa == ISA_MIPS32R2 \
|| mips_opts.isa == ISA_MIPS32R3 \
|| mips_opts.isa == ISA_MIPS32R5 \
|| mips_opts.isa == ISA_MIPS32R6 \
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.isa == ISA_MIPS64R3 \
|| mips_opts.isa == ISA_MIPS64R5 \
|| mips_opts.isa == ISA_MIPS64R6 \
|| mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_R5900 \
|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_R14000 \
|| mips_opts.arch == CPU_R16000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
|| mips_opts.micromips \
)
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs after they are loaded from memory, and thus does not
require nops to be inserted. This applies to instructions marked
INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
level I and microMIPS mode instructions are always interlocked. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
|| mips_opts.arch == CPU_R3900 \
|| mips_opts.arch == CPU_R5900 \
|| mips_opts.micromips \
)
/* Whether the processor uses hardware interlocks to avoid delays
required by coprocessor instructions, and thus does not require
nops to be inserted. This applies to instructions marked
INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
instructions marked INSN_WRITE_COND_CODE and ones marked
INSN_READ_COND_CODE. These nops are only required at MIPS ISA
levels I, II, and III and microMIPS mode instructions are always
interlocked. */
/* Itbl support may require additional care here. */
#define cop_interlocks \
((mips_opts.isa != ISA_MIPS1 \
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
|| mips_opts.micromips \
)
/* Whether the processor uses hardware interlocks to protect reads
from coprocessor registers after they are loaded from memory, and
thus does not require nops to be inserted. This applies to
instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
requires at MIPS ISA level I and microMIPS mode instructions are
always interlocked. */
#define cop_mem_interlocks \
(mips_opts.isa != ISA_MIPS1 \
|| mips_opts.micromips \
)
/* Is this a mfhi or mflo instruction? */
#define MF_HILO_INSN(PINFO) \
((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
has been selected. This implies, in particular, that addresses of text
labels have their LSB set. */
#define HAVE_CODE_COMPRESSION \
((mips_opts.mips16 | mips_opts.micromips) != 0)
/* The minimum and maximum signed values that can be stored in a GPR. */
#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
#define GPR_SMIN (-GPR_SMAX - 1)
/* MIPS PIC level. */
enum mips_pic_level mips_pic;
/* 1 if we should generate 32 bit offsets from the $gp register in
SVR4_PIC mode. Currently has no meaning in other modes. */
static int mips_big_got = 0;
/* 1 if trap instructions should used for overflow rather than break
instructions. */
static int mips_trap = 0;
/* 1 if double width floating point constants should not be constructed
by assembling two single width halves into two single width floating
point registers which just happen to alias the double width destination
register. On some architectures this aliasing can be disabled by a bit
in the status register, and the setting of this bit cannot be determined
automatically at assemble time. */
static int mips_disable_float_construction;
/* Non-zero if any .set noreorder directives were used. */
static int mips_any_noreorder;
/* Non-zero if nops should be inserted when the register referenced in
an mfhi/mflo instruction is read in the next two instructions. */
static int mips_7000_hilo_fix;
/* The size of objects in the small data section. */
static unsigned int g_switch_value = 8;
/* Whether the -G option was used. */
static int g_switch_seen = 0;
#define N_RMASK 0xc4
#define N_VFP 0xd4
/* If we can determine in advance that GP optimization won't be
possible, we can skip the relaxation stuff that tries to produce
GP-relative references. This makes delay slot optimization work
better.
This function can only provide a guess, but it seems to work for
gcc output. It needs to guess right for gcc, otherwise gcc
will put what it thinks is a GP-relative instruction in a branch
delay slot.
I don't know if a fix is needed for the SVR4_PIC mode. I've only
fixed it for the non-PIC mode. KR 95/04/07 */
static int nopic_need_relax (symbolS *, int);
/* Handle of the OPCODE hash table. */
static htab_t op_hash = NULL;
/* The opcode hash table we use for the mips16. */
static htab_t mips16_op_hash = NULL;
/* The opcode hash table we use for the microMIPS ASE. */
static htab_t micromips_op_hash = NULL;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
const char comment_chars[] = "#";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output. */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
/* Also note that C style comments are always supported. */
const char line_comment_chars[] = "#";
/* This array holds machine specific line separator characters. */
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums. */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant.
As in 0f12.456
or 0d1.2345e12. */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
changed in read.c . Ideally it shouldn't have to know about it at all,
but nothing is ideal around here. */
/* Types of printf format used for instruction-related error messages.
"I" means int ("%d") and "S" means string ("%s"). */
enum mips_insn_error_format
{
ERR_FMT_PLAIN,
ERR_FMT_I,
ERR_FMT_SS,
};
/* Information about an error that was found while assembling the current
instruction. */
struct mips_insn_error
{
/* We sometimes need to match an instruction against more than one
opcode table entry. Errors found during this matching are reported
against a particular syntactic argument rather than against the
instruction as a whole. We grade these messages so that errors
against argument N have a greater priority than an error against
any argument < N, since the former implies that arguments up to N
were acceptable and that the opcode entry was therefore a closer match.
If several matches report an error against the same argument,
we only use that error if it is the same in all cases.
min_argnum is the minimum argument number for which an error message
should be accepted. It is 0 if MSG is against the instruction as
a whole. */
int min_argnum;
/* The printf()-style message, including its format and arguments. */
enum mips_insn_error_format format;
const char *msg;
union
{
int i;
const char *ss[2];
} u;
};
/* The error that should be reported for the current instruction. */
static struct mips_insn_error insn_error;
static int auto_align = 1;
/* When outputting SVR4 PIC code, the assembler needs to know the
offset in the stack frame from which to restore the $gp register.
This is set by the .cprestore pseudo-op, and saved in this
variable. */
static offsetT mips_cprestore_offset = -1;
/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
more optimizations, it can use a register value instead of a memory-saved
offset and even an other register than $gp as global pointer. */
static offsetT mips_cpreturn_offset = -1;
static int mips_cpreturn_register = -1;
static int mips_gp_register = GP;
static int mips_gprel_offset = 0;
/* Whether mips_cprestore_offset has been set in the current function
(or whether it has already been warned about, if not). */
static int mips_cprestore_valid = 0;
/* This is the register which holds the stack frame, as set by the
.frame pseudo-op. This is needed to implement .cprestore. */
static int mips_frame_reg = SP;
/* Whether mips_frame_reg has been set in the current function
(or whether it has already been warned about, if not). */
static int mips_frame_reg_valid = 0;
/* To output NOP instructions correctly, we need to keep information
about the previous two instructions. */
/* Whether we are optimizing. The default value of 2 means to remove
unneeded NOPs and swap branch instructions when possible. A value
of 1 means to not swap branches. A value of 0 means to always
insert NOPs. */
static int mips_optimize = 2;
/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
equivalent to seeing no -g option at all. */
static int mips_debug = 0;
/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
#define MAX_VR4130_NOPS 4
/* The maximum number of NOPs needed to fill delay slots. */
#define MAX_DELAY_NOPS 2
/* The maximum number of NOPs needed for any purpose. */
#define MAX_NOPS 4
/* The maximum range of context length of ll/sc. */
#define MAX_LLSC_RANGE 20
/* A list of previous instructions, with index 0 being the most recent.
We need to look back MAX_NOPS instructions when filling delay slots
or working around processor errata. We need to look back one
instruction further if we're thinking about using history[0] to
fill a branch delay slot. */
static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE];
/* The maximum number of LABELS detect for the same address. */
#define MAX_LABELS_SAME 10
/* Arrays of operands for each instruction. */
#define MAX_OPERANDS 6
struct mips_operand_array
{
const struct mips_operand *operand[MAX_OPERANDS];
};
static struct mips_operand_array *mips_operands;
static struct mips_operand_array *mips16_operands;
static struct mips_operand_array *micromips_operands;
/* Nop instructions used by emit_nop. */
static struct mips_cl_insn nop_insn;
static struct mips_cl_insn mips16_nop_insn;
static struct mips_cl_insn micromips_nop16_insn;
static struct mips_cl_insn micromips_nop32_insn;
/* Sync instructions used by insert sync. */
static struct mips_cl_insn sync_insn;
/* The appropriate nop for the current mode. */
#define NOP_INSN (mips_opts.mips16 \
? &mips16_nop_insn \
: (mips_opts.micromips \
? (mips_opts.insn32 \
? µmips_nop32_insn \
: µmips_nop16_insn) \
: &nop_insn))
/* The size of NOP_INSN in bytes. */
#define NOP_INSN_SIZE ((mips_opts.mips16 \
|| (mips_opts.micromips && !mips_opts.insn32)) \
? 2 : 4)
/* If this is set, it points to a frag holding nop instructions which
were inserted before the start of a noreorder section. If those
nops turn out to be unnecessary, the size of the frag can be
decreased. */
static fragS *prev_nop_frag;
/* The number of nop instructions we created in prev_nop_frag. */
static int prev_nop_frag_holds;
/* The number of nop instructions that we know we need in
prev_nop_frag. */
static int prev_nop_frag_required;
/* The number of instructions we've seen since prev_nop_frag. */
static int prev_nop_frag_since;
/* Relocations against symbols are sometimes done in two parts, with a HI
relocation and a LO relocation. Each relocation has only 16 bits of
space to store an addend. This means that in order for the linker to
handle carries correctly, it must be able to locate both the HI and
the LO relocation. This means that the relocations must appear in
order in the relocation table.
In order to implement this, we keep track of each unmatched HI
relocation. We then sort them so that they immediately precede the
corresponding LO relocation. */
struct mips_hi_fixup
{
/* Next HI fixup. */
struct mips_hi_fixup *next;
/* This fixup. */
fixS *fixp;
/* The section this fixup is in. */
segT seg;
};
/* The list of unmatched HI relocs. */
static struct mips_hi_fixup *mips_hi_fixup_list;
/* Map mips16 register numbers to normal MIPS register numbers. */
static const unsigned int mips16_to_32_reg_map[] =
{
16, 17, 2, 3, 4, 5, 6, 7
};
/* Map microMIPS register numbers to normal MIPS register numbers. */
#define micromips_to_32_reg_d_map mips16_to_32_reg_map
/* The microMIPS registers with type h. */
static const unsigned int micromips_to_32_reg_h_map1[] =
{
5, 5, 6, 4, 4, 4, 4, 4
};
static const unsigned int micromips_to_32_reg_h_map2[] =
{
6, 7, 7, 21, 22, 5, 6, 7
};
/* The microMIPS registers with type m. */
static const unsigned int micromips_to_32_reg_m_map[] =
{
0, 17, 2, 3, 16, 18, 19, 20
};
#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
/* Classifies the kind of instructions we're interested in when
implementing -mfix-vr4120. */
enum fix_vr4120_class
{
FIX_VR4120_MACC,
FIX_VR4120_DMACC,
FIX_VR4120_MULT,
FIX_VR4120_DMULT,
FIX_VR4120_DIV,
FIX_VR4120_MTHILO,
NUM_FIX_VR4120_CLASSES
};
/* ...likewise -mtrap-zero-jump. */
static bfd_boolean mips_trap_zero_jump;
/* ...likewise -mfix-loongson2f-jump. */
static bool mips_fix_loongson2f_jump;
/* ...likewise -mfix-loongson2f-nop. */
static bool mips_fix_loongson2f_nop;
/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
static bool mips_fix_loongson2f;
/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
there must be at least one other instruction between an instruction
of type X and an instruction of type Y. */
static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
/* True if -mfix-vr4120 is in force. */
static int mips_fix_vr4120;
/* ...likewise -mfix-vr4130. */
static int mips_fix_vr4130;
/* ...likewise -mfix-24k. */
static int mips_fix_24k;
/* ...likewise -mfix-rm7000 */
static int mips_fix_rm7000;
/* ...likewise -mfix-cn63xxp1 */
static bool mips_fix_cn63xxp1;
/* ...likewise -mfix-r5900 */
static bool mips_fix_r5900;
static bool mips_fix_r5900_explicit;
/* ...likewise -mfix-loongson3-llsc. */
static bool mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC;
/* We don't relax branches by default, since this causes us to expand
`la .l2 - .l1' if there's a branch between .l1 and .l2, because we
fail to compute the offset before expanding the macro to the most
efficient expansion. */
static int mips_relax_branch;
static int mips_fix_loongson2f_btb;
/* TRUE if checks are suppressed for invalid branches between ISA modes.
Needed for broken assembly produced by some GCC versions and some
sloppy code out there, where branches to data labels are present. */
static bool mips_ignore_branch_isa;
/* The expansion of many macros depends on the type of symbol that
they refer to. For example, when generating position-dependent code,
a macro that refers to a symbol may have two different expansions,
one which uses GP-relative addresses and one which uses absolute
addresses. When generating SVR4-style PIC, a macro may have
different expansions for local and global symbols.
We handle these situations by generating both sequences and putting
them in variant frags. In position-dependent code, the first sequence
will be the GP-relative one and the second sequence will be the
absolute one. In SVR4 PIC, the first sequence will be for global
symbols and the second will be for local symbols.