-
Notifications
You must be signed in to change notification settings - Fork 2
/
README
258 lines (191 loc) · 8.43 KB
/
README
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
Router CAM installation
01. Xilinx Application
Router design requires two different XILINX TCAM modules. Obtain ‘xapp1151’ application from XILINX website. The tested CAM version is v1_1. As of the time of writing this document, the following link has the design files and its document of xapp1151.
http://www.xilinx.com/support/documentation/application_notes/xapp1151_Param_CAM.pdf
https://secure.xilinx.com/webreg/clickthrough.do?cid=154257
Please note that xilinx ISE must be installed to generate the core. Tested ISE version is 13.3.
02. Tool installation
On a directory you prefer, run:
tar xfvz xapp1151_cam_v1_1.tar.gz
03. First CAM module generation
cd xapp1151_cam_v1_1/implement
xilperl CustomizeWrapper.pl
You need to specify several parameters. To choose those options, see follows:
***************************************************************
CAM Reference Design Customizer v1.1
***************************************************************
***************************************************************
Please input the following parameters for the CAM:
***************************************************************
Enter the FPGA base architecture to target
Valid options are virtex4, virtex5, virtex6, virtex6l, spartan3, spartan3e, spartan3a, spartan3adsp, aspartan3, aspartan3e, spartan6:
virtex5
Input the CAM data width. Valid values are 1-512:
32
Input the CAM depth. Valid values are 16-4096:
32
Enter the CAM memory type to implement
(Choose SRL-based if you need a Ternary or Enhanced Ternary mode CAM)
0 = SRL-based, 1 = BRAM-based: 0
Choose the Ternary Mode setting.
0 = Ternary Mode Off, 1 = Standard Ternary Mode, 2 = Enhanced Ternary Mode: 1
Will the CAM be write-able (WE pin)? (If no, CAM will be read-only) (y/n): y
Use a MIF file to initialize the memory contents? (y/n): n
Choose what type of encoding the MATCH_ADDR port will have.
0 = Binary Encoded, 1 = Single Match Unencoded (one-hot), 2 = Multi-match Unencoded: 1
For Binary Encoded or Single Match Unencoded MATCH_ADDR, output lowest address match or highest address match?
0 = Lowest, 1 = Highest: 0
Please select the optional features to be implemented:
Simultaneous Read/Write (y/n): y
Please select from the following optional input ports:
Enable (EN) (y/n): n
Please select from the following optional output ports:
Multiple Match Flag (MULTIPLE_MATCH) (y/n): n
Single Match Flag (SINGLE_MATCH) (y/n): n
Read Warning Flag (READ_WARNING) (y/n): n
After the selections the parameters should be as follows:
VHDL parameters were generated as follows:
===============================================
C_FAMILY : string := virtex5;
C_MEM_TYPE : integer := 0;
C_WIDTH : integer := 32;
C_DEPTH : integer := 16;
C_ADDR_TYPE : integer := 1;
C_MATCH_RESOLUTION_TYPE : integer := 0;
C_TERNARY_MODE : integer := 1;
C_HAS_WE : integer := 1;
C_MEM_INIT : integer := 0;
C_HAS_CMP_DIN : integer := 1;
C_REG_OUTPUTS : integer := 0;
C_HAS_EN : integer := 0;
C_HAS_MULTIPLE_MATCH : integer := 0;
C_HAS_SINGLE_MATCH : integer := 0;
C_HAS_READ_WARNING : integer := 0;
===============================================
Then in the same directory, edit vhdl_xst.scr so that parameters are as follows:
-ifmt VHDL
-work_lib cam
-p xc5vtx240t-ff1759-2
-write_timing_constraints No
-ifn vhdl_xst.prj
-iobuf NO
-max_fanout 100
-ofn ./results/tcam.ngc
-ofmt NGC
-bufg 1
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
-opt_mode Speed
-opt_level 1
-loop_iteration_limit 5000
-use_new_parser yes
Then run:
xilperl RunXST.pl
04. Verilog file for simulation/implementation
After finishing above, run follows to create a verilog file for simulations:
cd results
netgen -sim -ofmt verilog tcam.ngc
Edit the created tcam.v file.
(1) Change the module name to ‘tcam’ from ‘cam_wrapper’.
(2) Just after the port declaration, write a sentence:
// synthesis translate_off
(3) And before endmodule of ‘cam_wrapper’, write;
// synthesis translate_on
Please note the file has two modules therefore two ‘endmodule’. Make sure to insert the line for the first module; cam_wrapper (now the module name is ‘tcam’).
05. File copy
Copy tcam.ngc in netlist directory of Router pcore:
cp tcam.ngc $(NF10_ROOT_DIRECTORY)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/netlist
Copy tcam.v in verilog directory of Router pcore:
cp tcam.v $(NF10_ROOT_DIRECTORY)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/hdl/verilog
06. Second CAM module generation.
xilperl CustomizeWrapper.pl
You need to specify several parameters. To choose those options, see follows:
***************************************************************
CAM Reference Design Customizer v1.1
***************************************************************
***************************************************************
Please input the following parameters for the CAM:
***************************************************************
Enter the FPGA base architecture to target
Valid options are virtex4, virtex5, virtex6, virtex6l, spartan3, spartan3e, spartan3a, spartan3adsp, aspartan3, aspartan3e, spartan6:
virtex5
Input the CAM data width. Valid values are 1-512:
32
Input the CAM depth. Valid values are 16-4096:
32
Enter the CAM memory type to implement
(Choose SRL-based if you need a Ternary or Enhanced Ternary mode CAM)
0 = SRL-based, 1 = BRAM-based: 1
NOTE: BRAM-based CAMs do not support Ternary Modes.
Setting C_TERNARY_MODE = 0 ...
Will the CAM be write-able (WE pin)? (If no, CAM will be read-only) (y/n): y
Use a MIF file to initialize the memory contents? (y/n): n
Choose what type of encoding the MATCH_ADDR port will have.
0 = Binary Encoded, 1 = Single Match Unencoded (one-hot), 2 = Multi-match Unencoded: 1
For Binary Encoded or Single Match Unencoded MATCH_ADDR, output lowest address match or highest address match?
0 = Lowest, 1 = Highest: 0
Please select the optional features to be implemented:
Simultaneous Read/Write (y/n): y
Register Outputs (y/n): n
Please select from the following optional input ports:
Enable (EN) (y/n): n
Please select from the following optional output ports:
Multiple Match Flag (MULTIPLE_MATCH) (y/n): n
Single Match Flag (SINGLE_MATCH) (y/n): n
Read Warning Flag (READ_WARNING) (y/n): n
After the selections the parameters should be as follows:
VHDL parameters were generated as follows:
===============================================
C_FAMILY : string := virtex5;
C_MEM_TYPE : integer := 1;
C_WIDTH : integer := 32;
C_DEPTH : integer := 16;
C_ADDR_TYPE : integer := 1;
C_MATCH_RESOLUTION_TYPE : integer := 0;
C_TERNARY_MODE : integer := 0;
C_HAS_WE : integer := 1;
C_MEM_INIT : integer := 0;
C_HAS_CMP_DIN : integer := 1;
C_REG_OUTPUTS : integer := 0;
C_HAS_EN : integer := 0;
C_HAS_MULTIPLE_MATCH : integer := 0;
C_HAS_SINGLE_MATCH : integer := 0;
C_HAS_READ_WARNING : integer := 0;
===============================================
Then in the same directory, edit vhdl_xst.scr so that parameters are as follows:
-ifmt VHDL
-work_lib cam
-p xc5vtx240t-ff1759-2
-write_timing_constraints No
-ifn vhdl_xst.prj
-iobuf NO
-max_fanout 100
-ofn ./results/cam.ngc
-ofmt NGC
-bufg 1
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
-opt_mode Speed
-opt_level 1
-loop_iteration_limit 5000
-use_new_parser yes
Then run:
xilperl RunXST.pl
07. Verilog file for simulation/implementation
After finishing above, run follows to create a verilog file for simulations:
cd results
netgen -sim -ofmt verilog cam.ngc
Edit the created cam.v file.
(1) Change the module name to ‘cam’ from ‘cam_wrapper’.
(2) Just after the port declaration, write a sentence:
// synthesis translate_off
(3) And before endmodule of ‘cam_wrapper’, write;
// synthesis translate_on
Please note the file has two modules therefore two ‘endmodule’. Make sure to insert the line for the first module; cam_wrapper (now the module name is ‘cam’).
08. File copy
Copy cam.ngc in netlist directory of Router pcore:
cp cam.ngc $(NF10_ROOT_DIRECTORY)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/netlist
Copy cam.v in verilog directory of Router pcore:
cp cam.v $(NF10_ROOT_DIRECTORY)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/hdl/verilog