notebooks/01_parse_and_dump.ipynb

{
 "cells": [
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {},
   "outputs": [],
   "source": [
    "import os\n",
    "import sys\n",
    "\n",
    "from hdlConvertorAst.language import Language\n",
    "from hdlConvertor import HdlConvertor\n",
    "\n",
    "TEST_DIR = os.path.join(\"..\", \"tests\", \"verilog\")\n",
    "\n",
    "filenames = [os.path.join(TEST_DIR, \"dff_async_reset.v\"), ]\n",
    "include_dirs = []\n",
    "c = HdlConvertor()\n",
    "# note that there is also Language.VERILOG_2005, Language.SYSTEM_VERILOG_2017 and others\n",
    "d = c.parse(filenames, Language.VERILOG, include_dirs, hierarchyOnly=False, debug=True)\n",
    "\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "// http://www.asic-world.com/code/hdl_models/dff_async_reset.v\n",
      "//-----------------------------------------------------\n",
      "// Design Name : dff_async_reset\n",
      "// File Name   : dff_async_reset.v\n",
      "// Function    : D flip-flop async reset\n",
      "// Coder       : Deepak Kumar Tala\n",
      "//-----------------------------------------------------\n",
      "module dff_async_reset (\n",
      "    //-----------Input Ports---------------\n",
      "    input wire data,\n",
      "    // Data Input\n",
      "    input wire clk,\n",
      "    // Clock Input\n",
      "    input wire reset,\n",
      "    // Reset input\n",
      "    //-----------Output Ports---------------\n",
      "    //------------Internal Variables--------\n",
      "    output reg q\n",
      ");\n",
      "    //-------------Code Starts Here---------\n",
      "    always @(posedge clk, negedge reset)\n",
      "        if (~reset)\n",
      "            q <= 1'b0;\n",
      "        else\n",
      "            q <= data;\n",
      "endmodule\n"
     ]
    }
   ],
   "source": [
    "from hdlConvertorAst.to.verilog.verilog2005 import ToVerilog2005\n",
    "\n",
    "tv = ToVerilog2005(sys.stdout)\n",
    "tv.visit_HdlContext(d)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "[\n",
      "    {\n",
      "        \"__class__\": \"HdlModuleDef\",\n",
      "        \"dec\": {\n",
      "            \"__class__\": \"HdlModuleDec\",\n",
      "            \"declaration_only\": false,\n",
      "            \"doc\": {\n",
      "                \"__class__\": \"str\",\n",
      "                \"val\": \" http://www.asic-world.com/code/hdl_models/dff_async_reset.v\\n-----------------------------------------------------\\n Design Name : dff_async_reset\\n File Name   : dff_async_reset.v\\n Function    : D flip-flop async reset\\n Coder       : Deepak Kumar Tala\\n-----------------------------------------------------\\n\"\n",
      "            },\n",
      "            \"name\": {\n",
      "                \"__class__\": \"str\",\n",
      "                \"val\": \"dff_async_reset\"\n",
      "            },\n",
      "            \"objs\": [],\n",
      "            \"params\": [],\n",
      "            \"ports\": [\n",
      "                {\n",
      "                    \"__class__\": \"HdlIdDef\",\n",
      "                    \"direction\": \"IN\",\n",
      "                    \"doc\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \"-----------Input Ports---------------\\n\"\n",
      "                    },\n",
      "                    \"name\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \"data\"\n",
      "                    },\n",
      "                    \"position\": [\n",
      "                        9,\n",
      "                        1,\n",
      "                        9,\n",
      "                        4\n",
      "                    ],\n",
      "                    \"type\": \"wire\"\n",
      "                },\n",
      "                {\n",
      "                    \"__class__\": \"HdlIdDef\",\n",
      "                    \"direction\": \"IN\",\n",
      "                    \"doc\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \" Data Input\\n\"\n",
      "                    },\n",
      "                    \"name\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \"clk\"\n",
      "                    },\n",
      "                    \"position\": [\n",
      "                        10,\n",
      "                        1,\n",
      "                        10,\n",
      "                        3\n",
      "                    ],\n",
      "                    \"type\": \"wire\"\n",
      "                },\n",
      "                {\n",
      "                    \"__class__\": \"HdlIdDef\",\n",
      "                    \"direction\": \"IN\",\n",
      "                    \"doc\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \" Clock Input\\n\"\n",
      "                    },\n",
      "                    \"name\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \"reset\"\n",
      "                    },\n",
      "                    \"position\": [\n",
      "                        11,\n",
      "                        1,\n",
      "                        11,\n",
      "                        5\n",
      "                    ],\n",
      "                    \"type\": \"wire\"\n",
      "                },\n",
      "                {\n",
      "                    \"__class__\": \"HdlIdDef\",\n",
      "                    \"direction\": \"OUT\",\n",
      "                    \"doc\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \" Reset input\\n-----------Output Ports---------------\\n------------Internal Variables--------\\n\"\n",
      "                    },\n",
      "                    \"is_static\": true,\n",
      "                    \"name\": {\n",
      "                        \"__class__\": \"str\",\n",
      "                        \"val\": \"q\"\n",
      "                    },\n",
      "                    \"position\": [\n",
      "                        12,\n",
      "                        1,\n",
      "                        12,\n",
      "                        1\n",
      "                    ],\n",
      "                    \"type\": {\n",
      "                        \"__class__\": \"HdlOp\",\n",
      "                        \"fn\": \"PARAMETRIZATION\",\n",
      "                        \"ops\": [\n",
      "                            \"reg\",\n",
      "                            {\n",
      "                                \"__class__\": \"str\",\n",
      "                                \"val\": null\n",
      "                            },\n",
      "                            {\n",
      "                                \"__class__\": \"str\",\n",
      "                                \"val\": null\n",
      "                            }\n",
      "                        ]\n",
      "                    }\n",
      "                }\n",
      "            ],\n",
      "            \"position\": [\n",
      "                8,\n",
      "                1,\n",
      "                31,\n",
      "                9\n",
      "            ]\n",
      "        },\n",
      "        \"module_name\": \"dff_async_reset\",\n",
      "        \"name\": {\n",
      "            \"__class__\": \"str\",\n",
      "            \"val\": null\n",
      "        },\n",
      "        \"objs\": [\n",
      "            {\n",
      "                \"__class__\": \"HdlStmProcess\",\n",
      "                \"body\": {\n",
      "                    \"__class__\": \"HdlStmIf\",\n",
      "                    \"cond\": {\n",
      "                        \"__class__\": \"HdlOp\",\n",
      "                        \"fn\": \"NEG\",\n",
      "                        \"ops\": [\n",
      "                            \"reset\"\n",
      "                        ]\n",
      "                    },\n",
      "                    \"elifs\": [],\n",
      "                    \"if_false\": {\n",
      "                        \"__class__\": \"HdlStmBlock\",\n",
      "                        \"body\": [\n",
      "                            {\n",
      "                                \"__class__\": \"HdlStmAssign\",\n",
      "                                \"dst\": \"q\",\n",
      "                                \"is_blocking\": false,\n",
      "                                \"labels\": [],\n",
      "                                \"src\": \"data\"\n",
      "                            }\n",
      "                        ],\n",
      "                        \"join_t\": \"SEQ\",\n",
      "                        \"labels\": []\n",
      "                    },\n",
      "                    \"if_true\": {\n",
      "                        \"__class__\": \"HdlStmBlock\",\n",
      "                        \"body\": [\n",
      "                            {\n",
      "                                \"__class__\": \"HdlStmAssign\",\n",
      "                                \"dst\": \"q\",\n",
      "                                \"is_blocking\": false,\n",
      "                                \"labels\": [],\n",
      "                                \"src\": {\n",
      "                                    \"__class__\": \"HdlValueInt\",\n",
      "                                    \"base\": 2,\n",
      "                                    \"bits\": 1,\n",
      "                                    \"val\": \"0\"\n",
      "                                }\n",
      "                            }\n",
      "                        ],\n",
      "                        \"join_t\": \"SEQ\",\n",
      "                        \"labels\": []\n",
      "                    },\n",
      "                    \"labels\": []\n",
      "                },\n",
      "                \"doc\": {\n",
      "                    \"__class__\": \"str\",\n",
      "                    \"val\": \"-------------Code Starts Here---------\\n\"\n",
      "                },\n",
      "                \"labels\": [],\n",
      "                \"sensitivity\": [\n",
      "                    {\n",
      "                        \"__class__\": \"HdlOp\",\n",
      "                        \"fn\": \"RISING\",\n",
      "                        \"ops\": [\n",
      "                            \"clk\"\n",
      "                        ]\n",
      "                    },\n",
      "                    {\n",
      "                        \"__class__\": \"HdlOp\",\n",
      "                        \"fn\": \"FALLING\",\n",
      "                        \"ops\": [\n",
      "                            \"reset\"\n",
      "                        ]\n",
      "                    }\n",
      "                ]\n",
      "            }\n",
      "        ],\n",
      "        \"position\": [\n",
      "            8,\n",
      "            1,\n",
      "            31,\n",
      "            9\n",
      "        ]\n",
      "    }\n",
      "]\n"
     ]
    }
   ],
   "source": [
    "from hdlConvertorAst.to.json import ToJson\n",
    "import json\n",
    "tj = ToJson()\n",
    "j = tj.visit_HdlContext(d)\n",
    "# pretty print json\n",
    "print(json.dumps(j, sort_keys=True,\n",
    "                 indent=4, separators=(',', ': ')))"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "{'__class__': 'HdlModuleDef',\n",
      " 'dec': {'__class__': 'HdlModuleDec',\n",
      "         'declaration_only': False,\n",
      "         'doc': {'__class__': 'str',\n",
      "                 'val': ' '\n",
      "                        'http://www.asic-world.com/code/hdl_models/dff_async_reset.v\\n'\n",
      "                        '-----------------------------------------------------\\n'\n",
      "                        ' Design Name : dff_async_reset\\n'\n",
      "                        ' File Name   : dff_async_reset.v\\n'\n",
      "                        ' Function    : D flip-flop async reset\\n'\n",
      "                        ' Coder       : Deepak Kumar Tala\\n'\n",
      "                        '-----------------------------------------------------\\n'},\n",
      "         'name': {'__class__': 'str', 'val': 'dff_async_reset'},\n",
      "         'objs': [],\n",
      "         'params': [],\n",
      "         'ports': [{'__class__': 'HdlIdDef',\n",
      "                    'direction': 'IN',\n",
      "                    'doc': {'__class__': 'str',\n",
      "                            'val': '-----------Input Ports---------------\\n'},\n",
      "                    'name': {'__class__': 'str', 'val': 'data'},\n",
      "                    'position': (9, 1, 9, 4),\n",
      "                    'type': 'wire'},\n",
      "                   {'__class__': 'HdlIdDef',\n",
      "                    'direction': 'IN',\n",
      "                    'doc': {'__class__': 'str', 'val': ' Data Input\\n'},\n",
      "                    'name': {'__class__': 'str', 'val': 'clk'},\n",
      "                    'position': (10, 1, 10, 3),\n",
      "                    'type': 'wire'},\n",
      "                   {'__class__': 'HdlIdDef',\n",
      "                    'direction': 'IN',\n",
      "                    'doc': {'__class__': 'str', 'val': ' Clock Input\\n'},\n",
      "                    'name': {'__class__': 'str', 'val': 'reset'},\n",
      "                    'position': (11, 1, 11, 5),\n",
      "                    'type': 'wire'},\n",
      "                   {'__class__': 'HdlIdDef',\n",
      "                    'direction': 'OUT',\n",
      "                    'doc': {'__class__': 'str',\n",
      "                            'val': ' Reset input\\n'\n",
      "                                   '-----------Output Ports---------------\\n'\n",
      "                                   '------------Internal Variables--------\\n'},\n",
      "                    'is_static': True,\n",
      "                    'name': {'__class__': 'str', 'val': 'q'},\n",
      "                    'position': (12, 1, 12, 1),\n",
      "                    'type': {'__class__': 'HdlOp',\n",
      "                             'fn': 'PARAMETRIZATION',\n",
      "                             'ops': ['reg',\n",
      "                                     {'__class__': 'str', 'val': None},\n",
      "                                     {'__class__': 'str', 'val': None}]}}],\n",
      "         'position': (8, 1, 31, 9)},\n",
      " 'module_name': 'dff_async_reset',\n",
      " 'name': {'__class__': 'str', 'val': None},\n",
      " 'objs': [{'__class__': 'HdlStmProcess',\n",
      "           'body': {'__class__': 'HdlStmIf',\n",
      "                    'cond': {'__class__': 'HdlOp',\n",
      "                             'fn': 'NEG',\n",
      "                             'ops': ['reset']},\n",
      "                    'elifs': [],\n",
      "                    'if_false': {'__class__': 'HdlStmBlock',\n",
      "                                 'body': [{'__class__': 'HdlStmAssign',\n",
      "                                           'dst': 'q',\n",
      "                                           'is_blocking': False,\n",
      "                                           'labels': [],\n",
      "                                           'src': 'data'}],\n",
      "                                 'join_t': 'SEQ',\n",
      "                                 'labels': []},\n",
      "                    'if_true': {'__class__': 'HdlStmBlock',\n",
      "                                'body': [{'__class__': 'HdlStmAssign',\n",
      "                                          'dst': 'q',\n",
      "                                          'is_blocking': False,\n",
      "                                          'labels': [],\n",
      "                                          'src': {'__class__': 'HdlValueInt',\n",
      "                                                  'base': 2,\n",
      "                                                  'bits': 1,\n",
      "                                                  'val': '0'}}],\n",
      "                                'join_t': 'SEQ',\n",
      "                                'labels': []},\n",
      "                    'labels': []},\n",
      "           'doc': {'__class__': 'str',\n",
      "                   'val': '-------------Code Starts Here---------\\n'},\n",
      "           'labels': [],\n",
      "           'sensitivity': [{'__class__': 'HdlOp',\n",
      "                            'fn': 'RISING',\n",
      "                            'ops': ['clk']},\n",
      "                           {'__class__': 'HdlOp',\n",
      "                            'fn': 'FALLING',\n",
      "                            'ops': ['reset']}]}],\n",
      " 'position': (8, 1, 31, 9)}\n",
      "\n"
     ]
    }
   ],
   "source": [
    "# each HDL AST object __repr__ returns json like string\n",
    "for o in d.objs:\n",
    "    print(o)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "data\n",
      "clk\n",
      "reset\n",
      "q\n"
     ]
    }
   ],
   "source": [
    "from hdlConvertorAst.hdlAst import HdlModuleDef\n",
    "\n",
    "# print port names\n",
    "for o in d.objs:\n",
    "    if isinstance(o, HdlModuleDef):\n",
    "        for x in o.dec.ports:\n",
    "            print(x.name)\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 6,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "// http://www.asic-world.com/code/hdl_models/dff_async_reset.v\n",
      "//-----------------------------------------------------\n",
      "// Design Name : dff_async_reset\n",
      "// File Name   : dff_async_reset.v\n",
      "// Function    : D flip-flop async reset\n",
      "// Coder       : Deepak Kumar Tala\n",
      "//-----------------------------------------------------\n",
      "module dff_async_reset (\n",
      "    //-----------Input Ports---------------\n",
      "    input wire DATA,\n",
      "    // Data Input\n",
      "    input wire CLK,\n",
      "    // Clock Input\n",
      "    input wire RESET,\n",
      "    // Reset input\n",
      "    //-----------Output Ports---------------\n",
      "    //------------Internal Variables--------\n",
      "    output reg Q\n",
      ");\n",
      "    //-------------Code Starts Here---------\n",
      "    always @(posedge CLK, negedge RESET)\n",
      "        if (~RESET)\n",
      "            Q <= 1'b0;\n",
      "        else\n",
      "            Q <= DATA;\n",
      "endmodule\n"
     ]
    }
   ],
   "source": [
    "from hdlConvertorAst.to.hdl_ast_visitor import HdlAstVisitor\n",
    "from hdlConvertorAst.hdlAst import HdlValueId, HdlOp\n",
    "\n",
    "class PortNamesToUpperCase(HdlAstVisitor):\n",
    "    \"\"\"\n",
    "    Make port names upper case HDL AST\n",
    "\n",
    "    :note: this is just a stupid rewrite of all variable names to upper case\n",
    "    \"\"\"\n",
    "    def visit_HdlIdDef(self, o):\n",
    "        o.name = o.name.upper()\n",
    "\n",
    "    def visit_HdlStmProcess(self, o):\n",
    "        if o.sensitivity:\n",
    "            o.sensitivity = [self.visit_iHdlExpr(s) for s in o.sensitivity]\n",
    "        self.visit_iHdlStatement(o.body)\n",
    "\n",
    "    def visit_iHdlExpr(self, o):\n",
    "        if isinstance(o, HdlValueId):\n",
    "            return HdlValueId(o.val.upper(), obj=o.obj)\n",
    "        elif isinstance(o, HdlOp):\n",
    "            o.ops = [self.visit_iHdlExpr(s) for s in o.ops]\n",
    "            return o\n",
    "        else:\n",
    "            return super(PortNamesToUpperCase, self).visit_iHdlExpr(o)\n",
    "\n",
    "    def visit_HdlStmIf(self, o):\n",
    "        o.cond = self.visit_iHdlExpr(o.cond)\n",
    "        super(PortNamesToUpperCase, self).visit_HdlStmIf(o)\n",
    "\n",
    "    def visit_HdlStmAssign(self, o):\n",
    "        o.src = self.visit_iHdlExpr(o.src)\n",
    "        o.dst = self.visit_iHdlExpr(o.dst)\n",
    "\n",
    "PortNamesToUpperCase().visit_HdlContext(d)\n",
    "\n",
    "tv = ToVerilog2005(sys.stdout)\n",
    "tv.visit_HdlContext(d)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  }
 ],
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  "kernelspec": {
   "display_name": "Python 3",
   "language": "python",
   "name": "python3"
  },
  "language_info": {
   "codemirror_mode": {
    "name": "ipython",
    "version": 3
   },
   "file_extension": ".py",
   "mimetype": "text/x-python",
   "name": "python",
   "nbconvert_exporter": "python",
   "pygments_lexer": "ipython3",
   "version": "3.8.2"
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 },
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}