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bladerf-hosted.vhd
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bladerf-hosted.vhd
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-- Copyright (c) 2013 Nuand LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
architecture hosted_bladerf of bladerf is
attribute noprune : boolean ;
attribute keep : boolean ;
component nios_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
dac_MISO : in std_logic := 'X'; -- MISO
dac_MOSI : out std_logic; -- MOSI
dac_SCLK : out std_logic; -- SCLK
dac_SS_n : out std_logic_vector(1 downto 0); -- SS_n
spi_MISO : in std_logic := 'X'; -- MISO
spi_MOSI : out std_logic; -- MOSI
spi_SCLK : out std_logic; -- SCLK
spi_SS_n : out std_logic; -- SS_n
oc_i2c_scl_pad_o : out std_logic;
oc_i2c_scl_padoen_o : out std_logic;
oc_i2c_sda_pad_i : in std_logic;
oc_i2c_sda_pad_o : out std_logic;
oc_i2c_sda_padoen_o : out std_logic;
oc_i2c_arst_i : in std_logic;
oc_i2c_scl_pad_i : in std_logic;
gpio_export : out std_logic_vector(31 downto 0);
xb_gpio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
xb_gpio_out_port : out std_logic_vector(31 downto 0);
xb_gpio_dir_export : out std_logic_vector(31 downto 0);
command_serial_in : in std_logic ;
command_serial_out : out std_logic ;
correction_rx_phase_gain_export : out std_logic_vector(31 downto 0);
correction_tx_phase_gain_export : out std_logic_vector(31 downto 0);
rx_tamer_ts_sync_in : in std_logic;
rx_tamer_ts_sync_out : out std_logic ;
rx_tamer_ts_pps : in std_logic ;
rx_tamer_ts_clock : in std_logic ;
rx_tamer_ts_reset : in std_logic;
rx_tamer_ts_time : out std_logic_vector(63 downto 0) ;
tx_tamer_ts_sync_in : in std_logic;
tx_tamer_ts_sync_out : out std_logic ;
tx_tamer_ts_pps : in std_logic ;
tx_tamer_ts_clock : in std_logic ;
tx_tamer_ts_reset : in std_logic;
tx_tamer_ts_time : out std_logic_vector(63 downto 0);
vctcxo_tamer_tune_ref : in std_logic;
vctcxo_tamer_vctcxo_clock : in std_logic;
tx_trigger_ctl_in_port : in std_logic_vector(7 downto 0);
tx_trigger_ctl_out_port : out std_logic_vector(7 downto 0);
rx_trigger_ctl_in_port : in std_logic_vector(7 downto 0);
rx_trigger_ctl_out_port : out std_logic_vector(7 downto 0);
arbiter_request : in std_logic_vector(1 downto 0);
arbiter_granted : out std_logic_vector(1 downto 0) := (others => 'X');
arbiter_ack : in std_logic_vector(1 downto 0) := (others => 'X');
agc_dc_i_max_export : out std_logic_vector(15 downto 0);
agc_dc_i_mid_export : out std_logic_vector(15 downto 0);
agc_dc_i_min_export : out std_logic_vector(15 downto 0);
agc_dc_q_max_export : out std_logic_vector(15 downto 0);
agc_dc_q_mid_export : out std_logic_vector(15 downto 0);
agc_dc_q_min_export : out std_logic_vector(15 downto 0)
);
end component;
alias sys_rst is fx3_ctl(7) ;
alias tx_clock is c4_tx_clock ;
alias rx_clock is lms_rx_clock_out ;
-- Can be set from libbladeRF using bladerf_set_rx_mux()
type rx_mux_mode_t is (RX_MUX_NORMAL, RX_MUX_12BIT_COUNTER, RX_MUX_32BIT_COUNTER, RX_MUX_ENTROPY, RX_MUX_DIGITAL_LOOPBACK) ;
signal rx_mux_sel : unsigned(2 downto 0) ;
signal rx_mux_mode : rx_mux_mode_t ;
signal \80MHz\ : std_logic ;
signal \80MHz locked\ : std_logic ;
signal nios_gpio : std_logic_vector(31 downto 0) ;
signal nios_xb_gpio_in : std_logic_vector(31 downto 0) ;
signal nios_xb_gpio_out : std_logic_vector(31 downto 0) ;
signal nios_xb_gpio_dir : std_logic_vector(31 downto 0) ;
signal xb_gpio_dir : std_logic_vector(31 downto 0) ;
signal correction_rx_phase_gain : std_logic_vector(31 downto 0);
signal correction_tx_phase_gain : std_logic_vector(31 downto 0);
signal i2c_scl_in : std_logic ;
signal i2c_scl_out : std_logic ;
signal i2c_scl_oen : std_logic ;
signal i2c_sda_in : std_logic ;
signal i2c_sda_out : std_logic ;
signal i2c_sda_oen : std_logic ;
type fifo_t is record
aclr : std_logic ;
wclock : std_logic ;
wdata : std_logic_vector(31 downto 0) ;
wreq : std_logic ;
wempty : std_logic ;
wfull : std_logic ;
wused : std_logic_vector(11 downto 0) ;
rclock : std_logic ;
rdata : std_logic_vector(31 downto 0) ;
rreq : std_logic ;
rempty : std_logic ;
rfull : std_logic ;
rused : std_logic_vector(11 downto 0) ;
end record ;
signal rx_sample_fifo : fifo_t ;
signal tx_sample_fifo : fifo_t ;
signal rx_loopback_fifo : fifo_t ;
type meta_fifo_tx_t is record
aclr : std_logic ;
wclock : std_logic ;
wdata : std_logic_vector(31 downto 0) ;
wreq : std_logic ;
wempty : std_logic ;
wfull : std_logic ;
wused : std_logic_vector(4 downto 0) ;
rclock : std_logic ;
rdata : std_logic_vector(127 downto 0) ;
rreq : std_logic ;
rempty : std_logic ;
rfull : std_logic ;
rused : std_logic_vector(2 downto 0) ;
end record ;
signal tx_meta_fifo : meta_fifo_tx_t ;
type meta_fifo_rx_t is record
aclr : std_logic ;
wclock : std_logic ;
wdata : std_logic_vector(127 downto 0) ;
wreq : std_logic ;
wempty : std_logic ;
wfull : std_logic ;
wused : std_logic_vector(4 downto 0) ;
rclock : std_logic ;
rdata : std_logic_vector(31 downto 0) ;
rreq : std_logic ;
rempty : std_logic ;
rfull : std_logic ;
rused : std_logic_vector(6 downto 0) ;
end record ;
signal rx_meta_fifo : meta_fifo_rx_t ;
signal sys_rst_sync : std_logic ;
signal sys_rst_80M : std_logic ;
signal usb_speed : std_logic ;
signal usb_speed_rx : std_logic ;
signal usb_speed_tx : std_logic ;
signal tx_reset : std_logic ;
signal rx_reset : std_logic ;
signal pclk_tx_enable : std_logic ;
signal pclk_rx_enable : std_logic ;
signal tx_enable : std_logic ;
signal rx_enable : std_logic ;
signal meta_en_tx : std_logic ;
signal meta_en_rx : std_logic ;
signal meta_en_fx3 : std_logic ;
signal tx_timestamp : unsigned(63 downto 0) ;
signal rx_timestamp : unsigned(63 downto 0) ;
signal timestamp_sync : std_logic ;
signal rx_sample_i : signed(15 downto 0) ;
signal rx_sample_q : signed(15 downto 0) ;
signal rx_sample_valid : std_logic ;
signal rx_gen_mode : std_logic ;
signal rx_gen_i : signed(15 downto 0) ;
signal rx_gen_q : signed(15 downto 0) ;
signal rx_gen_valid : std_logic ;
signal rx_entropy_i : signed(15 downto 0) := (others =>'0') ;
signal rx_entropy_q : signed(15 downto 0) := (others =>'0') ;
signal rx_entropy_valid : std_logic := '0' ;
signal rx_loopback_i : signed(15 downto 0) := (others =>'0') ;
signal rx_loopback_q : signed(15 downto 0) := (others =>'0') ;
signal rx_loopback_valid : std_logic := '0' ;
signal rx_loopback_enabled : std_logic := '0' ;
signal tx_loopback_enabled : std_logic := '0' ;
signal tx_sample_raw_i : signed(15 downto 0);
signal tx_sample_raw_q : signed(15 downto 0);
signal tx_sample_raw_valid : std_logic;
signal tx_sample_i : signed(15 downto 0) ;
signal tx_sample_q : signed(15 downto 0) ;
signal tx_sample_valid : std_logic ;
signal fx3_gpif_in : std_logic_vector(31 downto 0) ;
signal fx3_gpif_out : std_logic_vector(31 downto 0) ;
signal fx3_gpif_oe : std_logic ;
signal fx3_ctl_in : std_logic_vector(12 downto 0) ;
signal fx3_ctl_out : std_logic_vector(12 downto 0) ;
signal fx3_ctl_oe : std_logic_vector(12 downto 0) ;
signal tx_underflow_led : std_logic ;
signal tx_underflow_count : unsigned(63 downto 0) ;
signal rx_overflow_led : std_logic ;
signal rx_overflow_count : unsigned(63 downto 0) ;
signal lms_rx_data_reg : signed(11 downto 0) ;
signal lms_rx_iq_select_reg : std_logic ;
signal rx_mux_i : signed(15 downto 0) ;
signal rx_mux_q : signed(15 downto 0) ;
signal rx_mux_valid : std_logic ;
signal rx_sample_corrected_i : signed(15 downto 0);
signal rx_sample_corrected_q : signed(15 downto 0);
signal rx_sample_corrected_valid : std_logic;
signal led1_blink : std_logic;
signal nios_sdo : std_logic;
signal nios_sdio : std_logic;
signal nios_sclk : std_logic;
signal nios_ss_n : std_logic_vector(1 downto 0);
signal xb_mode : std_logic_vector(1 downto 0);
signal correction_valid : std_logic;
signal correction_tx_phase : signed(15 downto 0);--to_signed(integer(round(real(2**Q_SCALE) * PHASE_OFFSET)),DC_WIDTH);
signal correction_tx_gain : signed(15 downto 0);--to_signed(integer(round(real(2**Q_SCALE) * DC_OFFSET_REAL)),DC_WIDTH);
signal correction_rx_phase : signed(15 downto 0);--to_signed(integer(round(real(2**Q_SCALE) * PHASE_OFFSET)),DC_WIDTH);
signal correction_rx_gain : signed(15 downto 0);--to_signed(integer(round(real(2**Q_SCALE) * DC_OFFSET_REAL)),DC_WIDTH);
signal command_serial_in : std_logic ;
signal command_serial_out : std_logic ;
constant FPGA_DC_CORRECTION : signed(15 downto 0) := to_signed(integer(0), 16);
signal fx3_pclk_pll : std_logic ;
signal fx3_pll_locked : std_logic ;
signal timestamp_req : std_logic ;
signal timestamp_ack : std_logic ;
signal fx3_timestamp : unsigned(63 downto 0) ;
signal rx_ts_reset : std_logic ;
signal tx_ts_reset : std_logic ;
-- Trigger Control interfaces
signal rx_trigger_ctl : std_logic_vector(7 downto 0);
signal tx_trigger_ctl : std_logic_vector(7 downto 0);
-- Trigger Control breakdown
alias rx_trigger_arm : std_logic is rx_trigger_ctl(0);
alias rx_trigger_fire : std_logic is rx_trigger_ctl(1);
alias rx_trigger_master : std_logic is rx_trigger_ctl(2);
alias rx_trigger_line : std_logic is mini_exp1;
alias tx_trigger_arm : std_logic is tx_trigger_ctl(0);
alias tx_trigger_fire : std_logic is tx_trigger_ctl(1);
alias tx_trigger_master : std_logic is tx_trigger_ctl(2);
alias tx_trigger_line : std_logic is mini_exp1;
signal tx_trigger_arm_sync : std_logic ;
-- Trigger Control readback interfaces
signal rx_trigger_ctl_rb : std_logic_vector(7 downto 0);
signal tx_trigger_ctl_rb : std_logic_vector(7 downto 0);
-- Arbiter signal
signal arbiter_request : std_logic_vector(1 downto 0);
signal arbiter_granted : std_logic_vector(1 downto 0);
signal arbiter_ack : std_logic_vector(1 downto 0);
-- AGC control signal
signal agc_en : std_logic ;
signal gain_inc_req : std_logic ;
signal gain_dec_req : std_logic ;
signal gain_rst_req : std_logic ;
signal gain_ack : std_logic ;
signal gain_nack : std_logic ;
signal gain_max : std_logic ;
signal rst_gains : std_logic ;
signal burst : std_logic ;
signal agc_lms_sdio : std_logic ;
signal agc_lms_sclk : std_logic ;
signal agc_lms_sen : std_logic ;
signal nios_lms_sdio : std_logic ;
signal nios_lms_sclk : std_logic ;
signal nios_lms_sen : std_logic ;
-- Trigger Control readback breakdown
alias rx_trigger_arm_rb : std_logic is rx_trigger_ctl_rb(0);
alias rx_trigger_fire_rb : std_logic is rx_trigger_ctl_rb(1);
alias rx_trigger_master_rb : std_logic is rx_trigger_ctl_rb(2);
alias rx_trigger_line_rb : std_logic is rx_trigger_ctl_rb(3);
alias tx_trigger_arm_rb : std_logic is tx_trigger_ctl_rb(0);
alias tx_trigger_fire_rb : std_logic is tx_trigger_ctl_rb(1);
alias tx_trigger_master_rb : std_logic is tx_trigger_ctl_rb(2);
alias tx_trigger_line_rb : std_logic is tx_trigger_ctl_rb(3);
-- Trigger Outputs
signal lms_rx_enable_sig : std_logic;
signal lms_rx_enable_qualified : std_logic;
signal tx_sample_fifo_rempty_untriggered : std_logic;
-- AGC signals
signal agc_arbiter_req : std_logic;
signal agc_arbiter_grant : std_logic;
signal agc_arbiter_done : std_logic;
signal agc_band_sel : std_logic;
signal agc_gain_high : std_logic;
signal agc_gain_mid : std_logic;
signal agc_gain_low : std_logic;
signal fpga_dc_i_correction : signed(15 downto 0);
signal fpga_dc_q_correction : signed(15 downto 0);
signal corr_dc_i_max : std_logic_vector(15 downto 0);
signal corr_dc_i_mid : std_logic_vector(15 downto 0);
signal corr_dc_i_min : std_logic_vector(15 downto 0);
signal corr_dc_q_max : std_logic_vector(15 downto 0);
signal corr_dc_q_mid : std_logic_vector(15 downto 0);
signal corr_dc_q_min : std_logic_vector(15 downto 0);
begin
correction_tx_phase <= signed(correction_tx_phase_gain(31 downto 16));
correction_tx_gain <= signed(correction_tx_phase_gain(15 downto 0));
correction_rx_phase <= signed(correction_rx_phase_gain(31 downto 16));
correction_rx_gain <= signed(correction_rx_phase_gain(15 downto 0));
correction_valid <= '1';
-- Create 80MHz from 38.4MHz coming from the c4_clock source
U_pll : entity work.pll
port map (
inclk0 => c4_clock,
c0 => \80MHz\,
locked => \80MHz locked\
) ;
U_fx3_pll : entity work.fx3_pll
port map (
inclk0 => fx3_pclk,
c0 => fx3_pclk_pll,
locked => fx3_pll_locked
) ;
-- Cross domain synchronizer chains
U_usb_speed : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => fx3_pclk_pll,
async => nios_gpio(7),
sync => usb_speed
) ;
U_usb_speed_rx : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => rx_clock,
async => nios_gpio(7),
sync => usb_speed_rx
) ;
U_usb_speed_tx : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => tx_clock,
async => nios_gpio(7),
sync => usb_speed_tx
) ;
generate_mux_sel : for i in rx_mux_sel'range generate
U_rx_source : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => rx_clock,
async => nios_gpio(8+i),
sync => rx_mux_sel(i)
) ;
end generate ;
U_agc_en : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => rx_clock,
async => nios_gpio(12),
sync => agc_en
) ;
U_meta_sync_fx3 : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => fx3_pclk_pll,
async => nios_gpio(16),
sync => meta_en_fx3
) ;
U_meta_sync_tx : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => tx_clock,
async => nios_gpio(16),
sync => meta_en_tx
) ;
U_meta_sync_rx : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => '0',
clock => rx_clock,
async => nios_gpio(16),
sync => meta_en_rx
) ;
xb_mode <= nios_gpio(31 downto 30);
U_sys_reset_sync : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '1',
OUTPUT_LEVEL => '1'
) port map (
clock => fx3_pclk_pll,
async => sys_rst,
sync => sys_rst_sync
) ;
U_80M_reset_sync : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '1',
OUTPUT_LEVEL => '1'
) port map (
clock => \80MHz\,
async => sys_rst,
sync => sys_rst_80M
) ;
U_tx_reset : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '1',
OUTPUT_LEVEL => '1'
) port map (
clock => c4_tx_clock,
async => sys_rst_sync,
sync => tx_reset
) ;
U_rx_clock_reset : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '1',
OUTPUT_LEVEL => '1'
) port map (
clock => rx_clock,
async => sys_rst_sync,
sync => rx_reset
) ;
U_rx_enable_sync : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => rx_reset,
clock => rx_clock,
async => pclk_rx_enable,
sync => rx_enable
) ;
U_tx_enable_sync : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => tx_reset,
clock => tx_clock,
async => pclk_tx_enable,
sync => tx_enable
) ;
U_agc_arbiter_req_sync : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => sys_rst_80M,
clock => \80MHz\,
async => agc_arbiter_req,
sync => arbiter_request(1)
) ;
U_agc_arbiter_grant_sync : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => rx_reset,
clock => rx_clock,
async => arbiter_granted(1),
sync => agc_arbiter_grant
) ;
U_agc_arbiter_done_sync : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => sys_rst_80M,
clock => \80MHz\,
async => agc_arbiter_done,
sync => arbiter_ack(1)
) ;
U_agc_band_sel : entity work.synchronizer
generic map (
RESET_LEVEL => '0'
) port map (
reset => rx_reset,
clock => rx_clock,
async => nios_gpio(5),
sync => agc_band_sel
) ;
-- TX sample fifo
tx_sample_fifo.aclr <= tx_reset ;
tx_sample_fifo.wclock <= fx3_pclk_pll ;
tx_sample_fifo.rclock <= tx_clock ;
U_tx_sample_fifo : entity work.tx_fifo
port map (
aclr => tx_sample_fifo.aclr,
data => tx_sample_fifo.wdata,
rdclk => tx_sample_fifo.rclock,
rdreq => tx_sample_fifo.rreq,
wrclk => tx_sample_fifo.wclock,
wrreq => tx_sample_fifo.wreq,
q => tx_sample_fifo.rdata,
--rdempty => tx_sample_fifo.rempty,
rdempty => tx_sample_fifo_rempty_untriggered,
rdfull => tx_sample_fifo.rfull,
rdusedw => tx_sample_fifo.rused,
wrempty => tx_sample_fifo.wempty,
wrfull => tx_sample_fifo.wfull,
wrusedw => tx_sample_fifo.wused
);
-- TX meta fifo
tx_meta_fifo.aclr <= tx_reset ;
tx_meta_fifo.wclock <= fx3_pclk_pll ;
tx_meta_fifo.rclock <= tx_clock ;
U_tx_meta_fifo : entity work.tx_meta_fifo
port map (
aclr => tx_meta_fifo.aclr,
data => tx_meta_fifo.wdata,
rdclk => tx_meta_fifo.rclock,
rdreq => tx_meta_fifo.rreq,
wrclk => tx_meta_fifo.wclock,
wrreq => tx_meta_fifo.wreq,
q => tx_meta_fifo.rdata,
rdempty => tx_meta_fifo.rempty,
rdfull => tx_meta_fifo.rfull,
rdusedw => tx_meta_fifo.rused,
wrempty => tx_meta_fifo.wempty,
wrfull => tx_meta_fifo.wfull,
wrusedw => tx_meta_fifo.wused
);
-- RX sample fifo
rx_sample_fifo.wclock <= rx_clock ;
rx_sample_fifo.rclock <= fx3_pclk_pll ;
U_rx_sample_fifo : entity work.rx_fifo
port map (
aclr => "not"(pclk_rx_enable),
data => rx_sample_fifo.wdata,
rdclk => rx_sample_fifo.rclock,
rdreq => rx_sample_fifo.rreq,
wrclk => rx_sample_fifo.wclock,
wrreq => rx_sample_fifo.wreq,
q => rx_sample_fifo.rdata,
rdempty => rx_sample_fifo.rempty,
rdfull => rx_sample_fifo.rfull,
rdusedw => rx_sample_fifo.rused,
wrempty => rx_sample_fifo.wempty,
wrfull => rx_sample_fifo.wfull,
wrusedw => rx_sample_fifo.wused
);
-- RX meta fifo
rx_meta_fifo.aclr <= rx_reset ;
rx_meta_fifo.wclock <= rx_clock ;
rx_meta_fifo.rclock <= fx3_pclk_pll ;
U_rx_meta_fifo : entity work.rx_meta_fifo
port map (
aclr => "not"(pclk_rx_enable),
data => rx_meta_fifo.wdata,
rdclk => rx_meta_fifo.rclock,
rdreq => rx_meta_fifo.rreq,
wrclk => rx_meta_fifo.wclock,
wrreq => rx_meta_fifo.wreq,
q => rx_meta_fifo.rdata,
rdempty => rx_meta_fifo.rempty,
rdfull => rx_meta_fifo.rfull,
rdusedw => rx_meta_fifo.rused,
wrempty => rx_meta_fifo.wempty,
wrfull => rx_meta_fifo.wfull,
wrusedw => rx_meta_fifo.wused
);
-- RX loopback fifo
rx_loopback_fifo.aclr <= '1' when tx_reset = '1' or tx_loopback_enabled = '0' else '0' ;
rx_loopback_fifo.wclock <= tx_clock ;
rx_loopback_fifo.wdata <= std_logic_vector(tx_sample_i & tx_sample_q) when tx_loopback_enabled = '1' else (others => '0') ;
rx_loopback_fifo.wreq <= tx_sample_valid when tx_loopback_enabled = '1' else '0';
rx_loopback_fifo.rclock <= rx_clock ;
rx_loopback_fifo.rreq <= '1' when rx_loopback_enabled = '1' and rx_loopback_fifo.rempty = '0' else '0' ;
U_rx_loopack_fifo : entity work.rx_fifo
port map (
aclr => rx_loopback_fifo.aclr,
data => rx_loopback_fifo.wdata,
rdclk => rx_loopback_fifo.rclock,
rdreq => rx_loopback_fifo.rreq,
wrclk => rx_loopback_fifo.wclock,
wrreq => rx_loopback_fifo.wreq,
q => rx_loopback_fifo.rdata,
rdempty => rx_loopback_fifo.rempty,
rdfull => rx_loopback_fifo.rfull,
rdusedw => rx_loopback_fifo.rused,
wrempty => rx_loopback_fifo.wempty,
wrfull => rx_loopback_fifo.wfull,
wrusedw => rx_loopback_fifo.wused
);
U_loopback_sync : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '0',
OUTPUT_LEVEL => '0'
) port map (
clock => tx_clock,
async => rx_loopback_enabled,
sync => tx_loopback_enabled
) ;
rx_loopback_enabled <= '1' when rx_enable = '1' and rx_mux_mode = RX_MUX_DIGITAL_LOOPBACK else '0' ;
rx_loopback_i <= resize(signed(rx_loopback_fifo.rdata(31 downto 16)), rx_loopback_i'length) ;
rx_loopback_q <= resize(signed(rx_loopback_fifo.rdata(15 downto 0)), rx_loopback_q'length) ;
loopback_valid : process(rx_reset, rx_clock)
begin
if (rx_reset = '1') then
rx_loopback_valid <= '0';
elsif rising_edge(rx_clock) then
if (rx_loopback_fifo.rempty = '0') then
-- Delay fifo read request by one clock to indicate sample validity
rx_loopback_valid <= rx_loopback_fifo.rreq ;
else
rx_loopback_valid <= '0' ;
end if;
end if;
end process loopback_valid;
-- FX3 GPIF
U_fx3_gpif : entity work.fx3_gpif
port map (
pclk => fx3_pclk_pll,
reset => sys_rst_sync,
usb_speed => usb_speed,
meta_enable => meta_en_fx3,
rx_enable => pclk_rx_enable,
tx_enable => pclk_tx_enable,
gpif_in => fx3_gpif_in,
gpif_out => fx3_gpif_out,
gpif_oe => fx3_gpif_oe,
ctl_in => fx3_ctl_in,
ctl_out => fx3_ctl_out,
ctl_oe => fx3_ctl_oe,
tx_fifo_write => tx_sample_fifo.wreq,
tx_fifo_full => tx_sample_fifo.wfull,
tx_fifo_empty => tx_sample_fifo.wempty,
tx_fifo_usedw => tx_sample_fifo.wused,
tx_fifo_data => tx_sample_fifo.wdata,
tx_timestamp => fx3_timestamp,
tx_meta_fifo_write => tx_meta_fifo.wreq,
tx_meta_fifo_full => tx_meta_fifo.wfull,
tx_meta_fifo_empty => tx_meta_fifo.wempty,
tx_meta_fifo_usedw => tx_meta_fifo.wused,
tx_meta_fifo_data => tx_meta_fifo.wdata,
rx_fifo_read => rx_sample_fifo.rreq,
rx_fifo_full => rx_sample_fifo.rfull,
rx_fifo_empty => rx_sample_fifo.rempty,
rx_fifo_usedw => rx_sample_fifo.rused,
rx_fifo_data => rx_sample_fifo.rdata,
rx_meta_fifo_read => rx_meta_fifo.rreq,
rx_meta_fifo_full => rx_meta_fifo.rfull,
rx_meta_fifo_empty => rx_meta_fifo.rempty,
rx_meta_fifo_usedr => rx_meta_fifo.rused,
rx_meta_fifo_data => rx_meta_fifo.rdata
) ;
-- Sample bridges
U_fifo_writer : entity work.fifo_writer
port map (
clock => rx_clock,
reset => rx_reset,
enable => rx_enable,
usb_speed => usb_speed_rx,
meta_en => meta_en_rx,
timestamp => rx_timestamp,
fifo_clear => rx_sample_fifo.aclr,
fifo_full => rx_sample_fifo.wfull,
fifo_usedw => rx_sample_fifo.wused,
fifo_data => rx_sample_fifo.wdata,
fifo_write => rx_sample_fifo.wreq,
meta_fifo_full => rx_meta_fifo.wfull,
meta_fifo_usedw => rx_meta_fifo.wused,
meta_fifo_data => rx_meta_fifo.wdata,
meta_fifo_write => rx_meta_fifo.wreq,
in_i => rx_sample_corrected_i,
in_q => rx_sample_corrected_q,
in_valid => rx_sample_corrected_valid,
overflow_led => rx_overflow_led,
overflow_count => rx_overflow_count,
overflow_duration => x"ffff"
) ;
process(all)
begin
if( agc_gain_high = '1' ) then
fpga_dc_i_correction <= signed( corr_dc_i_max ) ;
fpga_dc_q_correction <= signed( corr_dc_q_max ) ;
elsif( agc_gain_mid = '1' ) then
fpga_dc_i_correction <= signed( corr_dc_i_mid ) ;
fpga_dc_q_correction <= signed( corr_dc_q_mid ) ;
elsif( agc_gain_low = '1' ) then
fpga_dc_i_correction <= signed( corr_dc_i_min ) ;
fpga_dc_q_correction <= signed( corr_dc_q_min ) ;
else
fpga_dc_i_correction <= ( others => '0' ) ;
fpga_dc_q_correction <= ( others => '0' ) ;
end if;
end process ;
U_rx_iq_correction : entity work.iq_correction(rx)
generic map(
INPUT_WIDTH => rx_sample_corrected_i'length
) port map(
reset => rx_reset,
clock => rx_clock,
in_real => resize(rx_mux_i,16),
in_imag => resize(rx_mux_q,16),
in_valid => rx_mux_valid,
out_real => rx_sample_corrected_i,
out_imag => rx_sample_corrected_q,
out_valid => rx_sample_corrected_valid,
dc_real => fpga_dc_i_correction,
dc_imag => fpga_dc_q_correction,
gain => correction_rx_gain,
phase => correction_rx_phase,
correction_valid => correction_valid
);
U_agc : entity work.bladerf_agc
port map (
clock => rx_clock,
reset => rx_reset,
agc_hold_req => '0',
gain_inc_req => gain_inc_req,
gain_dec_req => gain_dec_req,
gain_rst_req => gain_rst_req,
gain_ack => gain_ack,
gain_nack => gain_nack,
gain_max => gain_max,
rst_gains => rst_gains,
burst => burst,
sample_i => rx_sample_corrected_i,
sample_q => rx_sample_corrected_q,
sample_valid => rx_sample_corrected_valid
) ;
U_agc_lms : entity work.bladerf_agc_lms_drv
port map (
clock => rx_clock,
reset => rx_reset,
enable => agc_en,
gain_inc_req => gain_inc_req,
gain_dec_req => gain_dec_req,
gain_rst_req => gain_rst_req,
gain_ack => gain_ack,
gain_nack => gain_nack,
gain_high => agc_gain_high,
gain_mid => agc_gain_mid,
gain_low => agc_gain_low,
arbiter_req => agc_arbiter_req,
arbiter_grant => agc_arbiter_grant,
arbiter_done => agc_arbiter_done,
band_sel => agc_band_sel,
sclk => agc_lms_sclk,
miso => lms_sdo,
mosi => agc_lms_sdio,
cs_n => agc_lms_sen
) ;
U_agc_mux : process(all)
begin
if( arbiter_granted(1) = '1' ) then
lms_sdio <= agc_lms_sdio ;
lms_sclk <= agc_lms_sclk ;
lms_sen <= agc_lms_sen ;
else
lms_sdio <= nios_lms_sdio ;
lms_sclk <= nios_lms_sclk ;
lms_sen <= nios_lms_sen ;
end if ;
end process ;
U_fifo_reader : entity work.fifo_reader
port map (
clock => tx_clock,
reset => tx_reset,
enable => tx_enable,
usb_speed => usb_speed_tx,
meta_en => meta_en_tx,
timestamp => tx_timestamp,
fifo_empty => tx_sample_fifo.rempty,
fifo_usedw => tx_sample_fifo.rused,
fifo_data => tx_sample_fifo.rdata,
fifo_read => tx_sample_fifo.rreq,
meta_fifo_empty => tx_meta_fifo.rempty,
meta_fifo_usedw => tx_meta_fifo.rused,
meta_fifo_data => tx_meta_fifo.rdata,
meta_fifo_read => tx_meta_fifo.rreq,
out_i => tx_sample_raw_i,
out_q => tx_sample_raw_q,
out_valid => tx_sample_raw_valid,
underflow_led => tx_underflow_led,
underflow_count => tx_underflow_count,
underflow_duration => x"ffff"
) ;
U_tx_iq_correction : entity work.iq_correction(tx)
generic map (
INPUT_WIDTH => tx_sample_raw_i'length
) port map (
reset => tx_reset,
clock => tx_clock,
in_real => tx_sample_raw_i,
in_imag => tx_sample_raw_q,
in_valid => tx_sample_raw_valid,
out_real => tx_sample_i,
out_imag => tx_sample_q,
out_valid => tx_sample_valid,
dc_real => FPGA_DC_CORRECTION,
dc_imag => FPGA_DC_CORRECTION,
gain => correction_tx_gain,
phase => correction_tx_phase,
correction_valid => correction_valid
);
-- RX Trigger
rxtrig : entity work.trigger(async)
generic map (
DEFAULT_OUTPUT => '0'
) port map (
armed => rx_trigger_arm,
fired => rx_trigger_fire,
master => rx_trigger_master,
trigger_in => rx_trigger_line,
trigger_out => rx_trigger_line,
signal_in => lms_rx_enable_sig,
signal_out => lms_rx_enable_qualified
);
rx_trigger_arm_rb <= rx_trigger_arm;
rx_trigger_fire_rb <= rx_trigger_fire;
rx_trigger_master_rb <= rx_trigger_master;
rx_trigger_line_rb <= rx_trigger_line;
-- TX Trigger
U_tx_arm_sync : entity work.reset_synchronizer
generic map (
INPUT_LEVEL => '0',
OUTPUT_LEVEL => '0'
) port map (
clock => tx_clock,
async => tx_trigger_arm,
sync => tx_trigger_arm_sync
) ;
txtrig : entity work.trigger(async)
generic map (
DEFAULT_OUTPUT => '1'
) port map (
armed => tx_trigger_arm_sync,
fired => tx_trigger_fire,
master => tx_trigger_master,
trigger_in => tx_trigger_line,
trigger_out => tx_trigger_line,
signal_in => tx_sample_fifo_rempty_untriggered,
signal_out => tx_sample_fifo.rempty
);
tx_trigger_arm_rb <= tx_trigger_arm;
tx_trigger_fire_rb <= tx_trigger_fire;
tx_trigger_master_rb <= tx_trigger_master;
tx_trigger_line_rb <= tx_trigger_line;
-- LMS6002D IQ interface
rx_sample_i(15 downto 12) <= (others => rx_sample_i(11)) ;
rx_sample_q(15 downto 12) <= (others => rx_sample_q(11)) ;