Missing RX Samples

[kartarr]

A various number of rx samples is missing in the middle of the rx stream. The failure occurrence is irregular. The exact position needs more investigation work, but it seems to appear at the same position near 9000.
There is no rx overrun detected and no gap between the timestamps but the samples are missing. I would recommend to review the code and check points, where samples and meta data can get out of sync (caused i.e. by overrun ?)

Tested using sync interface

[kartarr]

Update:
I think the problem is the entity fifo_writer in the hdl code. Using block size of 256 samples the rx_sample_fifo length is 16 blocks, the meta fifo 32. It means, if the sample_fifo is full, the meta can be still stored. As I can see in the code, the meta_fifo_write signal does not handle the case, if sample fifo is full.

[bpadalino]

What is your current running samplerate? If you lower the samplerate does the problem go away? What versions of everything are you running? If you have a chance, can you try the dev-meta_support branch and try running the test_timestamps unit test from the build/output directory?

I see what you're talking about in the FPGA code. I'll take a look at that tonight and make sure that the metadata does not get written unless there is enough space for a full set of samples to go into the FIFO, and will drop samples at that point until there is enough space.

Does that sound reasonable?

[kartarr]

Perfect!
That's exactly what is happening here, the sample_fifo overruns, but the user see a nice timestamp log :-) Decreasing of the rx_meta_fifo depth to 8 solved the problem for me. But it's not a clean solution. The problem of detection is the rare occurrence depending on the current PC load. Probably is the sample rate of 3Msaps on the limit of my USB2.0 interface. I am not sure if the single test detects the problem but I will have a look.
I created the build of libbladerf and hdl from master today. FX3 comes from issue #255.

Thank you Brian

[kartarr]

I will continue testing, but here is my proposal how to change fifo_writer to fix the problem:
...

 type meta_reg_type is record
    data_go : std_logic;
    downcount : signed(12 downto 0);
    data : std_logic_vector(127 downto 0);
 end record;

signal overflow_recovering  :   std_logic ;
signal overflow_detected    :   std_logic ;
signal dma_buf_sz    : signed(12 downto 0);
signal meta_reg, meta_reg_in : meta_reg_type;

begin

 dma_buf_sz <= to_signed(507, dma_buf_sz'length) when usb_speed = '0' else to_signed(251, dma_buf_sz'length);

 meta_seq :process( clock)
begin
     if rising_edge(clock) then
        meta_reg <= meta_reg_in;
     end if;
end process;

 -- count down the metadata time
 meta_comb : process(meta_reg, reset, fifo_write, timestamp) 
     begin
        -- register
        meta_reg_in.data_go <= '0';
        meta_reg_in.data <= x"FFFFFFFF" & std_logic_vector(timestamp) & x"12344321";

        if (enable = '1' and meta_en = '1' and reset = '0') then 
            if (fifo_write = '0') then -- handle case rx_fifo is full
                meta_reg_in.downcount <= meta_reg.downcount;
            elsif ( meta_reg.downcount <= 0) then
                meta_reg_in.downcount <= dma_buf_sz;
                meta_reg_in.data_go <= '1';
            else
                meta_reg_in.downcount <= meta_reg.downcount - 1;
            end if;
        else
            meta_reg_in.downcount <= to_signed(0, dma_buf_sz'length);
        end if;

        -- output
        meta_fifo_data <= meta_reg.data;
        meta_fifo_write <= meta_reg.data_go;

    end process;

[jynik]

This has been addressed in FPGA v0.1.0