A35_BootBlock_0.4.8

bootblock 0.4.8

   https://github.com/Nuvoton-Israel/npcm8xx-bootblock/releases/tag/A35_BootBlock_0.4.8
   * set cntfrq_el0 should be after calling serial_printf_init.

signed-off-by: Tali Perry tali.perry@nuvoton.com

A35_BootBlock_0.4.7

bootblock 0.4.7

https://github.com/Nuvoton-Israel/npcm8xx-bootblock/releases/tag/A35_BootBlock_0.4.7
* Fix DDP\SDP type print.
* Cleanup code for upstream.
* Fix print of reset type for TIP reset case.
* Bug fix: when using dlls_trim_clk override from header option INCR bit value is set to bit 7 instead of 6. Fixed to 6.
* Add mode non-ECC ranges (8 total).
* Fix build on Linux (change "Apps" folder to "apps").
* Upgrade compiler and compile by default with dwarf-3 (allow debugging with Lauterbach, for GDB switch to -ggdb).
* Compile optimization for speed.
* Fix Coverity issues.
* Cleanup makefile.
* Add bit (over scratchpad bits): INTCR2.HOST_INIT  (bit 11). This bit indicates host is initialized by bootblock. After host is set bit is set to prevent re-init.
* Bug fix: cntfrq_el0 was set back to 25000000 after warm boot, regardless of CPU frequency.

signed-off-by: Tali Perry <tali.perry@nuvoton.com>

A35_BootBlock_0.4.6

Bootblock 0.4.6

• MC: Increase ECE priority to match VCD priority. Set ECE priority to 2.
• Fix errata: Errata fix: 1.7 eSPI FATAL_ERROR response

signed-off-by:tali.perry@nuvoton.com

A35_Bootblock_0.4.3

version 0.4.3 - Mar 4th 2024

• Bug fix: set cntfrq_el0 according to CPU frequency. Previously it was hard-coded to 250000000.

Bootblock 0.4.2

version 0.4.2 - Feb 28th 2024

• MC: modified default priority setting.
• Bug fix: PIXEL clock always connected to PLLG.
• Change CLK_750MHZ_PLLCON0_2_REG_CFG 0x003C2201
• Set DENALI_CTL_91_INLINE_ECC_BANK_OFFSET to 1.

signed-off-by:tali.perry@nuvoton.com

A35_BootBlock_0.4.1

Bootblock 0.4.1

version 0.4.1 - Feb 5th 2024

• Set PCI and GFX core clock to PLL1.

version 0.4.0 - Feb 1st 2024

• Bug fix: GMAC frequency always set to 125MHz.
• PCI always 125MHZ, RC always 100MHz.
• If ECC enabled, force both CPU and MC to be the same frequency.
• Add two optional GPIO set after mtest, declared in the IGPS header.

A35_BootBlock_0.3.9

Version 0.3.9 - Nov 29th 2023

• block PLL reseting in secondary boot. PLLs are set only after PORST.
  (PLLs only, other dividers like FIU are set on any reset, as requested by customers.
• Change print of DRAM type.
• Print all values in MHz (instead of Hz).

A35_BootBlock_0.3.8

version 0.3.8 - Nov 6th 2023

• bootblock output file rename back to arbel_a35_bootblock.bin.
• unused fuse data moved under ifdef
• Add 3 fields to header (FIU_DRD_CFG for fiu 0, 1, 3). User can change these values in IGPS. bootblock does not check
  value is legal.
• Cleanup makefile.

A35_BootBlock_0.3.7

Bootblock version 0.3.7

* Modify the Makefile to ensure compatibility with Linux compilation and incorporate a build.sh script.
* In NO_TIP mode: if training fails perform FSW to retry.
* In TIP mode: need to use TIP_FW 0.6.5 and up so that TIP will reset MC before bootblock to ensure no BMC access 
  during reset MC.
* Update timer driver with registers and basic functionality.
* Update FIU divider on every reset, according to the header.
* Set RDLEN to 0 on AHB6 and AHB13.

A35_BootBlock_0.3.6

version 0.3.6 - Oct 19th 2023

• Fix SPIX settings. SPIX should be below 33MHz. It was calculated according to SPI0 and not SPIX, and then set to SPIX.
• Read the DIE information from OTP and place it in SCRACHPAD 72 and 73, for the OPTEE to read it
• Bug fix: return pass status to TIP in secondary reset if training is skipped.