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clemency_processor.py
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clemency_processor.py
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# coding=utf-8
import pydevd
pydevd.settrace('localhost', port=15306, stdoutToServer=True, stderrToServer=True,suspend=False,overwrite_prev_trace=True,patch_multiprocessing=True)
from idaapi import *
from idc import *
import idautils
import copy
import ctypes
import bitstring
def SIGNEXT(x, b):
m = 1 << (b - 1)
m = 1 << (b - 1)
x = x & ((1 << b) - 1)
return (x ^ m) - m
def toInt(x):
return ctypes.c_int(x & 0xffffffff).value
EA_BITMASK = 0x7ffffff
FL_B = 0x000000001 # 8 bits
FL_W = 0x000000002 # 16 bits
FL_D = 0x000000004 # 32 bits
FL_Q = 0x000000008 # 64 bits
FL_OP1 = 0x000000010 # check operand 1
FL_32 = 0x000000020 # Is 32
FL_64 = 0x000000040 # Is 64
FL_NATIVE = 0x000000080 # native call (not EbcCal)
FL_REL = 0x000000100 # relative address
FL_CS = 0x000000200 # Condition flag is set
FL_NCS = 0x000000400 # Condition flag is not set
FL_INDIRECT = 0x000000800 # This is an indirect access (not immediate value)
FL_SIGNED = 0x000001000 # This is a signed operand
FL_MULTIREG = 0x000002000 # This is a multi reg operand
FL_HASUFFLAG = 0x000004000
FL_ABSOLUTE = 1 # absolute: &addr
FL_SYMBOLIC = 2 # symbolic: addr
o_regset = o_idpspec1
o_memflags = o_idpspec2
PR_TINFO = 0x20000000 # not present in python??
class DecodingError(Exception):
pass
class openrisc_processor_hook_t(IDP_Hooks):
def __init__(self):
IDP_Hooks.__init__(self)
def decorate_name3(self, name, mangle, cc):
gen_decorate_name3(name, mangle, cc)
return name
def calc_retloc3(self, rettype, cc, retloc):
if not rettype.is_void():
retloc._set_reg1(10)
return 1
def calc_varglocs3(self, ftd, regs, stkargs, nfixed):
return 1
def calc_arglocs3(self, fti):
self.calc_retloc3(fti.rettype, 0, fti.retloc)
n = fti.size()
for i in xrange(0, n):
if i > 7:
return -1
fti[i].argloc.set_reg1(10 + i, 0)
fti.stkargs = 0
return 2
def use_stkarg_type3(self, ea, arg):
return 0
def use_arg_types3(self, ea, fti, rargs):
gen_use_arg_tinfos(ea, fti, rargs)
return 2
def calc_purged_bytes3(self, p_purged_bytes, fti):
p_purged_bytes = 0
return 2
class clemency_data_type(data_type_t):
def __init__(self):
data_type_t.__init__(self, name="cLEMENCy",
value_size = 2, menu_name = "cLEMENCy string",
asm_keyword = ".clemency")
def calc_item_size(self, ea, maxsize):
# Custom data types may be used in structure definitions. If this case
# ea is a member id. Check for this situation and return 1
if is_member_id(ea):
return 1
ea_end = ea
while ea_end - ea < maxsize:
if not isLoaded(ea_end):
break
if Byte(ea_end) == 0:
break
ea_end += 1
return ea_end - ea + 1
class clemency_data_format(data_format_t):
FORMAT_NAME = "cLEMENCy string"
def __init__(self):
data_format_t.__init__(self, name=clemency_data_format.FORMAT_NAME)
def printf(self, value, current_ea, operand_num, dtid):
# Take the length byte
retsize = get_item_size(current_ea)
if retsize <= 0:
return 0
retsize -= 1
buf = GetManyBytes(current_ea,retsize * 2)
temp_buf = '"' + buf.decode('utf-16-le') + '", 0'
temp_buf = temp_buf.replace('\r', '", 0Dh, "').replace('\n','", 0Ah, "').replace('"", ','')
return temp_buf.encode("utf-8")
class clemency_tribyte_format(data_format_t):
FORMAT_NAME = "cLEMENCy tribyte"
def __init__(self):
data_format_t.__init__(self, name="cLEMENCy tribyte",
value_size = 3,
menu_name = "Correct Middle Endian",
hotkey = "Shift-M")
def printf(self, value, current_ea, operand_num, dtid):
# Take the length byte
byte1 = get_full_byte(current_ea) & 0x1ff
byte2 = get_full_byte(current_ea+1) & 0x1ff
byte3 = get_full_byte(current_ea+2) & 0x1ff
simplified = byte2 << 18 | byte1 << 9 | byte3
if isEnabled(simplified):
ua_add_dref(0,simplified,dr_R)
return "MIDDLE_ENDIAN(%Xh)" % (simplified)
new_formats = [
(clemency_data_type(), clemency_data_format()),
(clemency_tribyte_format(),),
#(0,clemency_tribyte_format())
]
class openrisc_processor_t(processor_t):
# id = 0x8001 + 0x5571C
id = 243
# flag = PR_SEGS | PRN_HEX | PR_RNAMESOK | PR_NO_SEGMOVE | PR_TINFO | PR_TYPEINFO
flag = PR_SEGS | PRN_HEX | PR_RNAMESOK | PR_NO_SEGMOVE
cnbits = 9
dnbits = 9
author = "Tea Deliverers"
psnames = ["cLEMENCy"]
plnames = ["cLEMENCy"]
segreg_size = 0
instruc_start = 0
assembler = {
"flag": ASH_HEXF0 | ASD_DECF0 | ASO_OCTF5 | ASB_BINF0 | AS_N2CHR,
"uflag": 0,
"name": "cLEMENCy asm",
"origin": ".org",
"end": ".end",
"cmnt": ";",
"ascsep": '"',
"accsep": "'",
"esccodes": "\"'",
"a_ascii": ".ascii",
"a_byte": ".byte",
"a_word": ".word",
"a_3byte": ".tribyte",
#"a_dword": ".dword",
#"a_qword": ".qword",
"a_bss": "dfs %s",
"a_seg": "seg",
"a_curip": "PC",
"a_public": "",
"a_weak": "",
"a_extrn": ".extern",
"a_comdef": "",
"a_align": ".align",
"lbrace": "(",
"rbrace": ")",
"a_mod": "%",
"a_band": "&",
"a_bor": "|",
"a_xor": "^",
"a_bnot": "~",
"a_shl": "<<",
"a_shr": ">>",
"a_sizeof_fmt": "size %s",
}
reg_names = regNames = [
# 在这里填上寄存器的顺序
# 记得也要留着下面的两行哦
# virtual
"R0", "R1", "R2", "R3", "R4",
"R5", "R6", "R7", "R8", "R9",
"R10", "R11", "R12", "R13", "R14",
"R15", "R16", "R17", "R18", "R19",
"R20", "R21", "R22", "R23", "R24",
"R25", "R26", "R27", "R28", "ST",
"RA", "PC", "FL",
"CS", "DS"
]
instruc = instrs = [
# {'name': 'lui', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'lui rd,imm'},
# 在这里按照上面的格式添加指令~~
{'name': 'ad', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'AD RA, RB, RC'},
{'name': 'adc', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ADC RA, RB, RC + Carray_Bit'},
{'name': 'adci', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ADCI RA, RB, IMM'},
{'name': 'adcim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ADCIM RA, RB, IMM (54bit-reg'},
{'name': 'adcm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ra:ra+1 <- rb:rb+1 + rc:rc+1 + C_B'},
{'name': 'adf', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'add float num'},
{'name': 'adfm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': '54bit float number add(ra:ra+1 <- rb:rb+1 + rc:rc+1)'},
{'name': 'adi', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ra <- rb + imm'},
{'name': 'adim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': ''},
{'name': 'adm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': ''},
{'name': 'an', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ra <- rb & rc'},
{'name': 'ani', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ra <- rb & imm'},
{'name': 'anm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'ra:ra+1 <- rb:rb+1 & rc:rc+1'},
{'name': 'bn', 'feature': CF_JUMP | CF_USE1, 'cmt': 'NOT ZERO'},
{'name': 'be', 'feature': CF_JUMP | CF_USE1, 'cmt': 'zero'},
{'name': 'bl', 'feature': CF_JUMP | CF_USE1, 'cmt': 'LESS THAN'},
{'name': 'ble', 'feature': CF_JUMP | CF_USE1, 'cmt': '<='},
{'name': 'bg', 'feature': CF_JUMP | CF_USE1, 'cmt': '>'},
{'name': 'bge', 'feature': CF_JUMP | CF_USE1, 'cmt': '>='},
{'name': 'bno', 'feature': CF_JUMP | CF_USE1, 'cmt': 'not overflow'},
{'name': 'bo', 'feature': CF_JUMP | CF_USE1, 'cmt': 'overflow'},
{'name': 'bns', 'feature': CF_JUMP | CF_USE1, 'cmt': 'not signed'},
{'name': 'bs', 'feature': CF_JUMP | CF_USE1, 'cmt': 'signed'},
{'name': 'bsl', 'feature': CF_JUMP | CF_USE1, 'cmt': 'signed <'},
{'name': 'bsle', 'feature': CF_JUMP | CF_USE1, 'cmt': 'signed <='},
{'name': 'bsg', 'feature': CF_JUMP | CF_USE1, 'cmt': 'signed >'},
{'name': 'bsge', 'feature': CF_JUMP | CF_USE1, 'cmt': 'signed >='},
{'name': 'b', 'feature': CF_JUMP | CF_USE1 | CF_STOP, 'cmt': 'ALWAYS'},
{'name': 'bf', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'RA <- ~Rb'},
{'name': 'bfm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'RA:RA+1 <- ~RB:RB+1'},
{'name': 'br', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'always'},
{'name': 'brn', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'not zero'},
{'name': 'brl', 'feature': CF_USE1 | CF_JUMP, 'cmt': '<'},
{'name': 'brle', 'feature': CF_USE1 | CF_JUMP, 'cmt': '<='},
{'name': 'brg', 'feature': CF_USE1 | CF_JUMP, 'cmt': '>'},
{'name': 'brge', 'feature': CF_USE1 | CF_JUMP, 'cmt': '>='},
{'name': 'brno', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'not overflow'},
{'name': 'bro', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'verflow'},
{'name': 'brns', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'not signed'},
{'name': 'brs', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'signed'},
{'name': 'brsl', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'signed <'},
{'name': 'brsle', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'signed <='},
{'name': 'brsg', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'signed >'},
{'name': 'brsge', 'feature': CF_USE1 | CF_JUMP, 'cmt': 'signed >='},
{'name': 'bra', 'feature': CF_USE1 | CF_JUMP | CF_STOP, 'cmt': ''},
{'name': 'brr', 'feature': CF_USE1 | CF_JUMP | CF_STOP, 'cmt': ''},
##############
{'name': 'c', 'feature': CF_CALL | CF_USE1, 'cmt': 'Call Always'},
{'name': 'cn', 'feature': CF_CALL | CF_USE1, 'cmt': ' not zero'},
{'name': 'ce', 'feature': CF_CALL | CF_USE1, 'cmt': 'zero'},
{'name': 'cl', 'feature': CF_CALL | CF_USE1, 'cmt': '<'},
{'name': 'cle', 'feature': CF_CALL | CF_USE1, 'cmt': '<='},
{'name': 'cg', 'feature': CF_CALL | CF_USE1, 'cmt': '>'},
{'name': 'cge', 'feature': CF_CALL | CF_USE1, 'cmt': '>='},
{'name': 'cno', 'feature': CF_CALL | CF_USE1, 'cmt': 'not overflow'},
{'name': 'co', 'feature': CF_CALL | CF_USE1, 'cmt': 'overflow'},
{'name': 'cns', 'feature': CF_CALL | CF_USE1, 'cmt': 'not signed'},
{'name': 'cs', 'feature': CF_CALL | CF_USE1, 'cmt': 'signed'},
{'name': 'csl', 'feature': CF_CALL | CF_USE1, 'cmt': 'signed <'},
{'name': 'csle', 'feature': CF_CALL | CF_USE1, 'cmt': 'signed <='},
{'name': 'csg', 'feature': CF_CALL | CF_USE1, 'cmt': 'signed >'},
{'name': 'cge', 'feature': CF_CALL | CF_USE1, 'cmt': 'signed >='},
{'name': 'caa', 'feature': CF_CALL | CF_USE1, 'cmt': 'Call Absolute RA=PC+4 pc = location'},
{'name': 'car', 'feature': CF_CALL | CF_USE1, 'cmt': 'Call Relative CAR Offset'},
{'name': 'cm', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare CM rA, rB'},
{'name': 'cmf', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare Floating Point CMF rA, rB'},
{'name': 'cmfm', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare Floating Point Multi Reg CMFM rA, rB'},
{'name': 'cmi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare Immediate CMI rA, IMM'},
{'name': 'cmim', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare Immediate Multi Reg CMIM rA, IMM(ra:ra+1)'},
{'name': 'cmm', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Compare Multi Reg CMM rA, rB'},
#
{'name': 'cr', 'feature': CF_USE1 | CF_CALL, 'cmt': 'Call Register Conditional Always CRcc rA'},
{'name': 'crn', 'feature': CF_USE1 | CF_CALL, 'cmt': 'not zero'},
{'name': 'cre', 'feature': CF_USE1 | CF_CALL, 'cmt': 'zero'},
{'name': 'crl', 'feature': CF_USE1 | CF_CALL, 'cmt': '<'},
{'name': 'crle', 'feature': CF_USE1 | CF_CALL, 'cmt': '<='},
{'name': 'crg', 'feature': CF_USE1 | CF_CALL, 'cmt': '>'},
{'name': 'crge', 'feature': CF_USE1 | CF_CALL, 'cmt': '>='},
{'name': 'crno', 'feature': CF_USE1 | CF_CALL, 'cmt': 'not overflow'},
{'name': 'cro', 'feature': CF_USE1 | CF_CALL, 'cmt': 'overfow'},
{'name': 'crns', 'feature': CF_USE1 | CF_CALL, 'cmt': 'not signed'},
{'name': 'crs', 'feature': CF_USE1 | CF_CALL, 'cmt': 'signed'},
{'name': 'crsl', 'feature': CF_USE1 | CF_CALL, 'cmt': 's <'},
{'name': 'crsle', 'feature': CF_USE1 | CF_CALL, 'cmt': 's <='},
{'name': 'crsg', 'feature': CF_USE1 | CF_CALL, 'cmt': 's >'},
{'name': 'crsge', 'feature': CF_USE1 | CF_CALL, 'cmt': 's >='},
#
{'name': 'dbrk', 'feature': CF_STOP, 'cmt': 'Debug Break DBRK'},
{'name': 'di', 'feature': CF_USE1, 'cmt': 'Disable Interrupts DI rA'},
{'name': 'dmt', 'feature': CF_USE1 | CF_USE2 | CF_USE3,
'cmt': 'copy data from [rb + p] to [ra + p] for rc times DMT rA, rB, rC'},
{'name': 'dv', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Divide DV rA, rB, rC'},
{'name': 'dvf', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Divide Floating Point DVF rA, rB, rC'},
{'name': 'dvfm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Divide Floating Point Multi Reg DVFM rA, rB, rC'},
{'name': 'dvi', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Divide Immediate DVI rA, rB, IMM'},
{'name': 'dvim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Divide Immediate Multi Reg DVIM rA, rB, IMM'},
{'name': 'dvis', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Divide Immediate Signed DVIS rA, rB, IMM'},
{'name': 'dvism', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Divide Immediate Signed Multi Reg DVISM rA, rB, IMM'},
{'name': 'dvm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Divide Multi Reg DVM rA, rB, rC'},
{'name': 'dvs', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Divide Signed DVS rA, rB, rC'},
{'name': 'dvsm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Divide Signed Multi Reg DVSM rA, rB, rC'},
{'name': 'ei', 'feature': CF_USE1, 'cmt': 'Enable Interrupts EI rA'},
#
{'name': 'fti', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Float to Integer ra <- (int)rb ;FTI rA, rB'},
{'name': 'ftim', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Float to Integer Multi Reg FTIM rA, rB'},
{'name': 'ht', 'feature': CF_STOP, 'cmt': 'Halt HT'},
{'name': 'ir', 'feature': CF_STOP, 'cmt': 'Interrupt Return IR'},
{'name': 'itf', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Integer to Float ITF rA, rB'},
{'name': 'itfm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Integer to Float Multi Reg ITFM rA, rB'},
# load
{'name': 'lds', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Single LDSm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'ldt', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Tri LDTm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'ldw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Word LDWm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'ldis', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Single LDSm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'ldit', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Tri LDTm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'ldiw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Word LDWm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'ldds', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Single LDSm rA, [rB + Offset, RegCount] (rB added)'},
{'name': 'lddt', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Tri LDTm rA, [rB + Offset, RegCount] (rB added)'},
{'name': 'lddw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Load Word LDWm rA, [rB + Offset, RegCount] (rB added)'},
{'name': 'md', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Modulus MD rA, rB, rC'},
{'name': 'mdf', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Modulus Floating Point MDF rA, rB, rC'},
{'name': 'mdfm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Modulus Floating Point Multi Reg MDFM rA, rB, rC'},
{'name': 'mdi', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Modulus Immediate MDI rA, rB, IMM'},
{'name': 'mdim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Modulus Immediate Multi Reg MDIM rA, rB, IMM'},
{'name': 'mdis', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Modulus Immediate Signed MDIS rA, rB, IMM'},
{'name': 'mdism', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Modulus Immediate Signed Multi Reg MDISM rA, rB, IMM'},
{'name': 'mdm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Modulus Multi Reg MDM rA, rB, rC'},
{'name': 'mds', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Modulus Signed MDS rA, rB, rC'},
{'name': 'mdsm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Modulus Signed Multi Reg MDSM rA, rB, rC'},
#
{'name': 'mh', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Move High MH rA, IMM'},
{'name': 'ml', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Move Low ML rA, IMM'},
{'name': 'ms', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Move Low Signed MS rA, IMM'},
{'name': 'mu', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Multiply MU rA, rB, rC'},
{'name': 'muf', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Floating Point MUF rA, rB, rC'},
{'name': 'mufm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Floating Point Multi Reg MUFM rA, rB, rC'},
{'name': 'mui', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Multiply Immediate MUI rA, rB, IMM'},
{'name': 'muim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Immediate Multi Reg MUIM rA, rB, IMM'},
{'name': 'muis', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Immediate Signed MUIS rA, rB, IMM'},
{'name': 'muism', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Immediate Signed Multi Reg MUISM rA, rB, IMM'},
{'name': 'mum', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Multiply Multi Reg MUM rA, rB, rC'},
{'name': 'mus', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Multiply Signed MUS rA, rB, rC'},
{'name': 'musm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Multiply Signed Multi Reg MUSM rA, rB, rC'},
#
{'name': 'ng', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Negate NG rA, rB'},
{'name': 'ngf', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Negate Floating Point NGF rA, rB'},
{'name': 'ngfm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1,
'cmt': 'Negate Floating Point Multi Reg NGFM rA, rB'},
{'name': 'ngm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Negate Multi Reg NGM rA, rB'},
{'name': 'nt', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Not NT rA, rB'},
{'name': 'ntm', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Not Multi Reg NTM rA, rB'},
# or
{'name': 'or', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Or OR rA, rB, rC'},
{'name': 'ori', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Or Immediate ORI rA, rB, IMM'},
{'name': 'orm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Or Multi Reg ORM rA, rB, rC'},
{'name': 're', 'feature': CF_STOP, 'cmt': 'Return RE'},
{'name': 'rf', 'feature': CF_USE1 | CF_STOP | CF_CHG1, 'cmt': 'Read Flags RF rA'},
{'name': 'rl', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Rotate Left RL rA, rB, rC'},
{'name': 'rli', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Left Immediate RLI rA, rB, IMM'},
{'name': 'rlim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Left Immediate Multi Reg RLIM rA, rB, IMM'},
{'name': 'rlm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Left Multi Reg RLM rA, rB, rC'},
{'name': 'rmp', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Read Memory Protection RMP rA, rB'},
{'name': 'rnd', 'feature': CF_USE1 | CF_CHG1, 'cmt': 'Random RND rA'},
{'name': 'rndm', 'feature': CF_USE1 | CF_CHG1, 'cmt': 'Random Multi Reg RNDM rA'},
{'name': 'rr', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Rotate Right RR rA, rB, rC'},
{'name': 'rri', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Right Immediate RRI rA, rB, IMM'},
{'name': 'rrim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Right Immediate Multi Reg RRIM rA, rB, rC'},
{'name': 'rrm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Rotate Right Multi Reg RRM rA, rB, rC'},
{'name': 'sa', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Arithemetic Right SA rA, rB, rC'},
{'name': 'sai', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Arithemetic Right Immediate SAI rA, rB, IMM'},
{'name': 'saim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Arithemetic Right Immediate Multi Reg SAIM rA, rB, IMM'},
{'name': 'sam', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Arithemetic Right Multi Reg SAM rA, rB, rC'},
{'name': 'sb', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Subtract SB rA, rB, rC'},
{'name': 'sbc', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Subtract With Carry SBC rA, rB, rC'},
{'name': 'sbci', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Immediate With Carry SBCI rA, rB, IMM'},
{'name': 'sbcim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Immediate Multi Reg With Carry SBCIM rA, rB, IMM'},
{'name': 'sbcm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Multi Reg With Carry SBCM rA, rB, rC'},
{'name': 'sbf', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Floating Point SBF rA, rB, rC'},
{'name': 'sbfm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Floating Point Multi Reg SBFM rA, rB, rC'},
{'name': 'sbi', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Subtract Immediate SBI rA, rB, IMM'},
{'name': 'sbim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Subtract Immediate Multi Reg SBIM rA, rB, IMM'},
{'name': 'sbm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Subtract Multi Reg SBM rA, rB, rC'},
{'name': 'ses', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Sign Extend Single SES rA, rB'},
{'name': 'sew', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Sign Extend Word SEW rA, rB'},
{'name': 'sf', 'feature': CF_USE1 | CF_USE2, 'cmt': 'Set Flags SF rA'},
{'name': 'sl', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Shift Left SL rA, rB, rC'},
{'name': 'sli', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Left Immediate SLI rA, rB, IMM'},
{'name': 'slim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Left Immediate Multi Reg SLIM rA, rB, IMM'},
{'name': 'slm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Left Multi Reg SLM rA, rB, rC'},
{'name': 'smp', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Set Memory Protection SMP rA, rB, FLAGS'},
{'name': 'sr', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Shift Right SR rA, rB, rC'},
{'name': 'sri', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Right Immediate SRI rA, rB, IMM'},
{'name': 'srim', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Right Immediate Multi Reg SRIM rA, rB, IMM'},
{'name': 'srm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1,
'cmt': 'Shift Right Multi Reg SRM rA, rB, rC'},
#
{'name': 'sts', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Single STSm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'stt', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Tri STTm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'stw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Word STWm rA, [rB + Offset, RegCount] (rB not modified)'},
{'name': 'stds', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Single STSm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'stdt', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Tri STTm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'stdw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Word STWm rA, [rB + Offset, RegCount] (rB substracted)'},
{'name': 'stis', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Single STSm rA, [rB + Offset, RegCount] '},
{'name': 'stit', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Tri STTm rA, [rB + Offset, RegCount] (rB added)'},
{'name': 'stiw', 'feature': CF_USE1 | CF_USE2 | CF_CHG1 | CF_CHG2,
'cmt': 'Store Word STWm rA, [rB + Offset, RegCount] (rB added)'},
#
{'name': 'wt', 'feature': 0, 'cmt': 'Wait WT'},
{'name': 'xr', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Xor XR rA, rB, rC'},
{'name': 'xri', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Xor Immediate XRI rA, rB, IMM'},
{'name': 'xrm', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_CHG1, 'cmt': 'Xor Multi Reg XRM rA, rB, rC'},
{'name': 'zes', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Zero Extend Single ZES rA, rB'},
{'name': 'zew', 'feature': CF_USE1 | CF_USE2 | CF_CHG1, 'cmt': 'Zero Extend Word ZEW rA, rB'}
]
ufnames = ["ad", "adc", "adci", "adcim", "adcm", "adf", "adfm", "adi", "adim", "adm", "an", "ani", "anm", "bf", "bfm", "dv",
"dvf", "dvfm", "dvi", "dvim", "dvis", "dvism", "dvm", "dvs", "dvsm", "md", "mdf", "mdfm", "mdi", "mdim", "mdis",
"mdism", "mdm", "mds", "mdsm", "mu", "muf", "mufm", "mui", "muim", "muis", "muism", "mum", "mus", "musm", "ng",
"ngf", "ngfm", "ngm", "nt", "ntm", "or", "ori", "orm", "rl", "rli", "rlim", "rlm", "rnd", "rndm", "rr", "rri",
"rrim", "rrm", "sa", "sai", "saim", "sam", "sb", "sbc", "sbci", "sbcim", "sbcm", "sbf", "sbfm", "sbi", "sbim",
"sbm", "sl", "sli", "slim", "slm", "sr", "sri", "srim", "srm", "xr", "xri", "xrm"]
instruc_end = len(instruc)
idphook = None
def __init__(self):
processor_t.__init__(self)
self._init_instructions()
self._init_registers()
self.last_ml_array = [{'reg': -1, 'value': 0}]
self.last_mh_array = [{'reg': -1, 'value': 0}]
def _init_instructions(self):
self.inames = {}
for idx, ins in enumerate(self.instrs):
self.inames[ins['name']] = idx
def _init_registers(self):
self.reg_ids = {}
for i, reg in enumerate(self.reg_names):
self.reg_ids[reg] = i
self.regFirstSreg = self.regCodeSreg = self.reg_ids["CS"]
self.regLastSreg = self.regDataSreg = self.reg_ids["DS"]
#
# Read a 9-bit byte
#
#
def _read_cmd_byte(self):
ea = self.cmd.ea + self.cmd.size
dword = get_full_byte(ea)
self.cmd.size += 1
return dword
def convertMiddleEndian(self, bits):
temp1 = bits[0:9]
temp2 = bits[9:18]
temp3 = bits[18:27]
return temp2 + temp1 + temp3
def _ana(self):
cmd = self.cmd
temp_opcode = bitstring.BitArray()
temp = bitstring.BitArray(length=9)
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
opcode = self.convertMiddleEndian(temp_opcode)
temp_opcode = bitstring.BitArray()
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
temp.uint = (self._read_cmd_byte() & 0x1ff)
temp_opcode += temp
opcode += self.convertMiddleEndian(temp_opcode)
# print hex(opcode.uint)
bitfield_0_12 = opcode[0:12].uint
bitfield_0_18 = opcode[0:18].uint
bitfield_0_5 = opcode[0:5].uint
bitfield_0_6 = opcode[0:6].uint
bitfield_0_7 = opcode[0:7].uint
bitfield_0_8 = opcode[0:8].uint
bitfield_0_9 = opcode[0:9].uint
bitfield_10_15 = opcode[10:15].uint
bitfield_10_27 = opcode[10:27].uint
bitfield_12_17 = opcode[12:17].uint
bitfield_13_18 = opcode[13:18].uint
bitfield_13_27 = opcode[13:27].uint
bitfield_14_19 = opcode[14:19].uint
bitfield_14_26 = opcode[14:26].uint
bitfield_15_18 = opcode[15:18].uint
bitfield_17_22 = opcode[17:22].uint
bitfield_17_24 = opcode[17:24].uint
bitfield_17_27 = opcode[17:27].uint
bitfield_18_20 = opcode[18:20].uint
bitfield_19_26 = opcode[19:26].uint
bitfield_19_27 = opcode[19:27].uint
bitfield_20_27 = opcode[20:27].uint
bitfield_22_24 = opcode[22:24].uint
bitfield_22_26 = opcode[22:26].uint
bitfield_22_27 = opcode[22:27].uint
bitfield_24_26 = opcode[24:26].uint
bitfield_24_51 = opcode[24:51].uint
bitfield_51_54 = opcode[51:54].uint
bitfield_5_10 = opcode[5:10].uint
bitfield_6_10 = opcode[6:10].uint
bitfield_7_12 = opcode[7:12].uint
bitfield_8_13 = opcode[8:13].uint
bitfield_9_14 = opcode[9:14].uint
bitfield_9_36 = opcode[9:36].uint
bitfield_17_18 = opcode[17:18].uint
bitfield_26_27 = opcode[26:27].uint # UF bit, ignored by us
if bitfield_0_7 == 0x0 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["ad"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x20 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["adc"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x20 and bitfield_24_26 == 0x1:
cmd.itype = self.inames["adci"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_imm
cmd[2].value = bitfield_17_24
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x22 and bitfield_24_26 == 0x1:
cmd.itype = self.inames["adcim"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_imm
cmd[2].value = bitfield_17_24
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x22 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["adcm"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x1 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["adf"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x3 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["adfm"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x0 and bitfield_24_26 == 0x1:
cmd.itype = self.inames["adi"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_imm
cmd[2].value = bitfield_17_24
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x2 and bitfield_24_26 == 0x1:
cmd.itype = self.inames["adim"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_imm
cmd[2].value = bitfield_17_24
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x2 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["adm"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x14 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["an"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x14 and bitfield_24_26 == 0x1:
cmd.itype = self.inames["ani"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_imm
cmd[2].value = bitfield_17_24
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_7 == 0x16 and bitfield_22_26 == 0x0:
cmd.itype = self.inames["anm"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_7_12
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_12_17
cmd[1].dtyp = dt_dword
cmd[2].type = o_reg
cmd[2].reg = bitfield_17_22
cmd[2].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0xf:
cmd.itype = self.inames["b"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x0:
cmd.itype = self.inames["bn"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x1:
cmd.itype = self.inames["be"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x2:
cmd.itype = self.inames["bl"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x3:
cmd.itype = self.inames["ble"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x4:
cmd.itype = self.inames["bg"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x5:
cmd.itype = self.inames["bge"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x6:
cmd.itype = self.inames["bno"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x7:
cmd.itype = self.inames["bo"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x8:
cmd.itype = self.inames["bns"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0x9:
cmd.itype = self.inames["bs"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0xa:
cmd.itype = self.inames["bsl"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0xb:
cmd.itype = self.inames["bsle"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0xc:
cmd.itype = self.inames["bsg"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x30 and bitfield_6_10 == 0xd:
cmd.itype = self.inames["bsge"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_9 == 0x14c and bitfield_19_26 == 0x40:
cmd.itype = self.inames["bf"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_9_14
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_14_19
cmd[1].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_9 == 0x14e and bitfield_19_26 == 0x40:
cmd.itype = self.inames["bfm"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_9_14
cmd[0].dtyp = dt_dword
cmd[1].type = o_reg
cmd[1].reg = bitfield_14_19
cmd[1].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0xf and bitfield_15_18 == 0x0:
cmd.itype = self.inames["br"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x0 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brn"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x1 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["bre"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x2 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brl"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x3 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brle"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x4 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brg"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x5 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brge"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x6 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brno"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x7 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["bro"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x8 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brns"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0x9 and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brs"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0xa and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brsl"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0xb and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brsle"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0xc and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brsg"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_6 == 0x32 and bitfield_6_10 == 0xd and bitfield_15_18 == 0x0:
cmd.itype = self.inames["brsge"]
cmd[0].type = o_reg
cmd[0].reg = bitfield_10_15
cmd[0].dtyp = dt_dword
opcode_size = 2
elif bitfield_0_9 == 0x1c4:
cmd.itype = self.inames["bra"]
opcode[27:36] = opcode[36:45]
cmd[0].type = o_near
cmd[0].addr = opcode[9:36].uint
cmd[0].dtyp = dt_dword
opcode_size = 4
elif bitfield_0_9 == 0x1c0:
cmd.itype = self.inames["brr"]
opcode[27:36] = opcode[36:45]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(opcode[9:36].uint, 27)
cmd[0].dtyp = dt_dword
opcode_size = 4
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0xf:
cmd.itype = self.inames["c"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0x0:
cmd.itype = self.inames["cn"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0x1:
cmd.itype = self.inames["ce"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0x2:
cmd.itype = self.inames["cl"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0x3:
cmd.itype = self.inames["cle"]
cmd[0].type = o_near
cmd[0].addr = cmd.ea + SIGNEXT(bitfield_10_27, 17)
cmd[0].dtyp = dt_dword
opcode_size = 3
elif bitfield_0_6 == 0x35 and bitfield_6_10 == 0x4:
cmd.itype = self.inames["cg"]