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Signed-off-by: MICHELE GAZZETTI <Michele.Gazzetti1@ibm.com>
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Resources/CXLAgent/AggregationService/ConnectionMethods/CXL/index.json
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{ | ||
"@odata.type": "#ConnectionMethod.v1_1_0.ConnectionMethod", | ||
"Id": "NVMeoF", | ||
"Name": "ConnectionMethod for Agent CXL", | ||
"ConnectionMethodType": "Redfish", | ||
"ConnectionMethodVariant": "Contoso", | ||
"Links": { | ||
"AggregationSources": [] | ||
}, | ||
"@odata.id": "/redfish/v1/AggregationService/ConnectionMethods/CXL" | ||
} |
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Resources/CXLAgent/AggregationService/ConnectionMethods/index.json
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{ | ||
"@odata.type": "#ConnectionMethodCollection.ConnectionMethodCollection", | ||
"Name": "ConnectionMethod Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/AggregationService/ConnectionMethods/CXL" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/ConnectionMethods", | ||
"@Redfish.Copyright": "Copyright 2015-2022 SNIA. All rights reserved." | ||
} |
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{ | ||
"@odata.type": "#AggregationService.v1_0_1.AggregationService", | ||
"Id": "AggregationService", | ||
"Name": "Aggregation Service", | ||
"Description": "Open Fabric Manager Aggregation Service", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK" | ||
}, | ||
"ServiceEnabled": true, | ||
|
||
"@odata.id": "/redfish/v1/AggregationService", | ||
"@Redfish.Copyright": "Copyright 2023 OpenFabrics Alliance. All rights reserved." | ||
} |
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{ | ||
"@odata.type": "#Chassis.v1_20_0.Chassis", | ||
"Id": "CXL-Chassis", | ||
"Name": "CXL System chassis containig CXL cards", | ||
"PowerState": "On", | ||
"ChassisType": "Blade", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"Links": { | ||
"ComputerSystems": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Systems/CXL-System" | ||
} | ||
], | ||
"Contains": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1" | ||
}, | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL2" | ||
}, | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL3" | ||
} | ||
] | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL-Chassis", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1/index.json
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{ | ||
"@odata.type": "#CXLLogicalDevice.v1_0_0.CXLLogicalDevice", | ||
"Id": "1", | ||
"Name": "CXL Logical Device Type 1", | ||
"Description": "Locally attached CXL Logical Device Type 1", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"Identifiers": [ | ||
{ | ||
"DurableName": "4C-1D-96-FF-FE-DD-D8-35:1", | ||
"DurableNameFormat": "GCXLID" | ||
} | ||
], | ||
"CXLSemanticsSupported": [ | ||
"CXLio", | ||
"CXLcache" | ||
], | ||
"Links": { | ||
"PCIeDevice": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" | ||
}, | ||
"PCIeFunctions": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" | ||
} | ||
], | ||
"Oem": {} | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/index.json
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{ | ||
"@odata.type": "#CXLLogicalDeviceCollection.CXLLogicalDeviceCollection", | ||
"Name": "CXL Logical Device Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1/index.json
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{ | ||
"@odata.type": "#PCIeFunction.v1_4_0.PCIeFunction", | ||
"Id": "1", | ||
"Name": "CXL Function", | ||
"Description": "PCIe Function with CXL extensions representing FPGA", | ||
"FunctionId": 1, | ||
"FunctionType": "Physical", | ||
"DeviceClass": "Processor", | ||
"DeviceId": "0xABCD", | ||
"VendorId": "0xABCD", | ||
"ClassCode": "0x0B4000", | ||
"RevisionId": "0x00", | ||
"SubsystemId": "0xABCD", | ||
"SubsystemVendorId": "0xABCD", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"FunctionProtocol": "CXL", | ||
"Links": { | ||
"Processors": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" | ||
} | ||
], | ||
"CXLLogicalDevice": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices/1" | ||
}, | ||
"PCIeDevice": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" | ||
} | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/index.json
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{ | ||
"@odata.type": "#PCIeFunctionCollection.PCIeFunctionCollection", | ||
"Name": "PCIe Function Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#PCIeDevice.v1_10_0.PCIeDevice", | ||
"Id": "1", | ||
"Name": "CXL Device", | ||
"Description": "CXL Physcial Device Type 1", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"PCIeInterface": { | ||
"PCIeType": "Gen5", | ||
"MaxPCIeType": "Gen5", | ||
"LanesInUse": 8, | ||
"MaxLanes": 16 | ||
}, | ||
"PCIeFunctions": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions" | ||
}, | ||
"CXLDevice":{ | ||
"CurrentProtocolVersion": "V2_0", | ||
"CapableProtocolVersion": "V2_0", | ||
"DeviceType": "Type1", | ||
"MultiLogicalDevice": false | ||
}, | ||
"CXLLogicalDevices": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/CXLLogicalDevices" | ||
}, | ||
"Links": { | ||
"Chassis": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1" | ||
} | ||
], | ||
"Oem": {} | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#PCIeDeviceCollection.PCIeDeviceCollection", | ||
"Name": "PCIe Device Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL1/Processors/FPGA/index.json
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{ | ||
"@odata.type": "#Processor.v1_15_0.Processor", | ||
"Id": "FPGA", | ||
"Name": "FPGA with cache", | ||
"Description": "FPGA with cache", | ||
"ProcessorType": "FPGA", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"ProcessorMemory": [ | ||
{ | ||
"IntegratedMemory": true, | ||
"MemoryType": "Cache", | ||
"CapacityMiB": 64 | ||
} | ||
], | ||
"MemorySummary": { | ||
"TotalMemorySizeMiB": 0, | ||
"TotalCacheSizeMiB": 64 | ||
}, | ||
"Links": { | ||
"PCIeFunctions": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices/1/PCIeFunctions/1" | ||
} | ||
], | ||
"ConnectedProcessors": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Systems/CXL-System/Processors/CPU" | ||
} | ||
] | ||
}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#ProcessorCollection.ProcessorCollection", | ||
"Name": "Processor Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/Processors/FPGA" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/Processors", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#Chassis.v1_20_0.Chassis", | ||
"Id": "CXL1", | ||
"Name": "CXL Device Type 1 module", | ||
"ChassisType": "Module", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK", | ||
"HealthRollup": "OK" | ||
}, | ||
"PCIeDevices": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/PCIeDevices" | ||
}, | ||
"Processors": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL1/Processors" | ||
}, | ||
"Links": { | ||
"ContainedBy": { | ||
"@odata.id": "/redfish/v1/Chassis/CXL-Chassis" | ||
} | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL1", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#Memory.v1_15_0.Memory", | ||
"Id": "HBM", | ||
"MemoryType": "DRAM", | ||
"MemoryDeviceType": "HBM2", | ||
"MemoryMedia": [ | ||
"DRAM" | ||
], | ||
"Name": "HBM memory", | ||
"CapacityMiB": 16384, | ||
"OperatingSpeedMhz": 1333, | ||
"Status": { | ||
"Health": "OK", | ||
"State": "Enabled", | ||
"HealthRollup": "OK" | ||
}, | ||
"Links": { | ||
"Processors": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/Processors/GPU" | ||
} | ||
] | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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{ | ||
"@odata.type": "#MemoryCollection.MemoryCollection", | ||
"Name": "Memory Collection", | ||
"Description": "Memory Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/Memory/HBM" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/Memory", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1/index.json
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{ | ||
"@odata.type": "#MemoryChunks.v1_5_0.MemoryChunks", | ||
"Id": "1", | ||
"Name": "Memory Chunk 1", | ||
"Description": "Memory chunk accessible through CXL", | ||
"Status": { | ||
"State": "Enabled", | ||
"Health": "OK" | ||
}, | ||
"MemoryChunkSizeMiB": 4096, | ||
"AddressRangeType": "Volatile", | ||
"AddressRangeOffsetMiB": 1024, | ||
"MediaLocation": "Local", | ||
"OperationalState": "Online", | ||
"Links": { | ||
"CXLLogicalDevices": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/PCIeDevices/1/CXLLogicalDevices/1" | ||
} | ||
] | ||
}, | ||
"Oem": {}, | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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Resources/CXLAgent/Chassis/CXL2/MemoryDomains/1/MemoryChunks/index.json
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{ | ||
"@odata.type": "#MemoryChunksCollection.MemoryChunksCollection", | ||
"Name": "Memory Chunks Collection", | ||
"Members@odata.count": 1, | ||
"Members": [ | ||
{ | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks/1" | ||
} | ||
], | ||
"@odata.id": "/redfish/v1/Chassis/CXL2/MemoryDomains/1/MemoryChunks", | ||
"@Redfish.Copyright": "Copyright 2014-2021 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright." | ||
} |
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