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Merge 00253a1 into 38a8534
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@anandaravuri
anandaravuri committed Oct 12, 2023
2 parents 38a8534 + 00253a1 commit 0cb8d95
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Showing 2 changed files with 76 additions and 44 deletions.
21 changes: 11 additions & 10 deletions samples/cxl_mem_tg/cxl_mem_tg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ namespace cxl_mem_tg {
using opae::fpga::types::token;
const char *AFU_ID = "4DADEA34-2C78-48CB-A3DC-5B831F5CECBB";

static const uint64_t MEM_TG_TEST_TIMEOUT = 30000;
static const uint64_t MEM_TG_TEST_TIMEOUT = 3000000;
static const uint64_t TEST_SLEEP_INVL = 100;
static const uint64_t TG_CTRL_CLEAR = 0x8000000000000000;
static const uint64_t TG_SLEEP = 300 / 1000;
Expand Down Expand Up @@ -80,7 +80,7 @@ enum {
MEM_TG_CTRL = 0x0030,
MEM_TG_STAT = 0x0038,
MEM_TG_CLK_COUNT = 0x0050,
MEM_TG_RD_COUNT = 0x0058,
MEM_TG_WR_COUNT = 0x0058,
MEM_TG_CLK_FREQ = 0x0060,
};
const int MEM_TG_CFG_OFFSET = 0x1000;
Expand Down Expand Up @@ -130,6 +130,7 @@ enum {
TG_PPPG_SEL = MEM_TG_CFG_OFFSET + 0x05C0,
TG_BYTEEN_SEL = MEM_TG_CFG_OFFSET + 0x0600,
TG_ADDR_FIELD_RELATIVE_FREQ = MEM_TG_CFG_OFFSET + 0x0640,
TG_ADDR_FIELD_MSB_INDEX = MEM_TG_CFG_OFFSET + 0x0680,
TG_BURSTLENGTH_OVERFLOW_OCCURRED = MEM_TG_CFG_OFFSET + 0x06C0,
TG_BURSTLENGTH_FAIL_ADDR_L = MEM_TG_CFG_OFFSET + 0x0700,
TG_BURSTLENGTH_FAIL_ADDR_H = MEM_TG_CFG_OFFSET + 0x0704,
Expand Down Expand Up @@ -171,7 +172,7 @@ union mem_tg0_count {

// Memory Traffic Generator count
union mem_tg1_count {
enum { offset = MEM_TG_RD_COUNT };
enum { offset = MEM_TG_WR_COUNT };
uint64_t value;
struct {
uint64_t count : 64;
Expand Down Expand Up @@ -199,17 +200,17 @@ class cxl_mem_tg : public test_afu {

// Loops
app_.add_option("--loops", loop_, "Number of read/write loops to be run")
->default_val("1");
->transform(CLI::Range(0, 268435456))->default_val(0);

// Writes
app_.add_option("-w,--writes", wcnt_,
"Number of unique write transactions per loop")
->default_val("1");
->transform(CLI::Range(0, 4095))->default_val(0);

// Reads
app_.add_option("-r,--reads", rcnt_,
"Number of unique read transactions per loop")
->default_val("1");
->transform(CLI::Range(0, 4095))->default_val("1");

// Address Stride
app_.add_option("--stride", stride_,
Expand Down Expand Up @@ -249,10 +250,10 @@ class cxl_mem_tg : public test_afu {
public:
uint32_t count_;
uint32_t mem_ch_;
uint32_t loop_;
uint32_t wcnt_;
uint32_t rcnt_;
uint32_t bcnt_;
uint64_t loop_;
uint64_t wcnt_;
uint64_t rcnt_;
uint64_t bcnt_;
uint32_t stride_;
uint32_t pattern_;
uint64_t mem_speed_;
Expand Down
99 changes: 65 additions & 34 deletions samples/cxl_mem_tg/cxl_tg_test.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@ class cxl_tg_test : public test_command {

// Convert number of transactions to bandwidth (GB/s)
double bw_calc(uint64_t xfer_bytes, uint64_t num_ticks) {
return (double)(xfer_bytes) /
return (double)(xfer_bytes)* 0.931323 /
((1000.0 / (double)(tg_exe_->mem_speed_/1000) * (double)num_ticks));
}

Expand All @@ -96,8 +96,8 @@ class cxl_tg_test : public test_command {
tg_exe_->logger_->debug("TG Status:0x{:x}", tg_exe_->read64(MEM_TG_STAT));
tg_exe_->logger_->debug("TG Total clock count:0x{:x}",
tg_exe_->read64(MEM_TG_CLK_COUNT));
tg_exe_->logger_->debug("TG read Clock Count:0x{:x}",
tg_exe_->read64(MEM_TG_RD_COUNT));
tg_exe_->logger_->debug("TG Write Clock Count:0x{:x}",
tg_exe_->read64(MEM_TG_WR_COUNT));
tg_exe_->logger_->debug("TG Frequency:{}", tg_exe_->read64(MEM_TG_CLK_FREQ));
tg_exe_->logger_->debug("TG_LOOP_COUNT:0x{:x}",
tg_exe_->read32(TG_LOOP_COUNT));
Expand Down Expand Up @@ -133,47 +133,59 @@ class cxl_tg_test : public test_command {
tg_exe_->logger_->debug("TG performance ...");

if (tg_exe_->status_ == TG_STATUS_TIMEOUT) {
std::cerr << "TG timeout" << std::endl;
cerr << "TG timeout" << endl;
} else if (tg_exe_->status_ == TG_STATUS_ERROR) {
uint32_t tg_fail_exp;
uint32_t tg_fail_act;
uint64_t tg_fail_addr;
tg_fail_addr = tg_exe_->read64(TG_FIRST_FAIL_ADDR_L);
tg_fail_exp = tg_exe_->read64(TG_FAIL_EXPECTED_DATA);
tg_fail_act = tg_exe_->read64(TG_FAIL_READ_DATA);
std::cerr << "TG status error" << std::endl;
std::cout << "Failed at address 0x" << std::hex << tg_fail_addr
cerr << "TG status error" << std::endl;
cout << "Failed at address 0x" << std::hex << tg_fail_addr
<< " exp=0x" << tg_fail_exp << " act=0x" << tg_fail_act
<< std::endl;
<< endl;
} else {
tg_exe_->logger_->debug("TG pass");
}

uint64_t clk_count = tg_exe_->read64(MEM_TG_CLK_COUNT);
std::cout << "TG Read and Write Clock Cycles: " << std::dec << clk_count
<< std::endl;
uint64_t rd_clk_count = tg_exe_->read64(MEM_TG_RD_COUNT);
std::cout << "TG Read Clock Cycles: " << std::dec << rd_clk_count << std::endl;
cout << "TG Read and Write Clock Cycles: " << dec << clk_count
<< endl;
uint64_t wr_clk_count = tg_exe_->read64(MEM_TG_WR_COUNT);
cout << "TG Write Clock Cycles: " << dec << wr_clk_count << endl;

uint64_t wr_clk_count = clk_count - rd_clk_count;
std::cout << "TG Write Clock Cycles: " << std::dec << wr_clk_count
<< std::endl;
uint64_t rd_clk_count = clk_count - wr_clk_count;
cout << "TG Read Clock Cycles: " << dec << rd_clk_count
<< endl;

uint64_t write_bytes =
64 * (tg_exe_->loop_ * tg_exe_->wcnt_ * tg_exe_->bcnt_);
uint64_t read_bytes =
64 * (tg_exe_->loop_ * tg_exe_->rcnt_ * tg_exe_->bcnt_);

std::cout << "Write bytes: " << std::dec << write_bytes
<< std::endl;
std::cout << "Read bytes: " << std::dec << read_bytes
<< std::endl;
std::cout << "Write BW: " << bw_calc(write_bytes, wr_clk_count) << " GB/s"
<< std::endl;
std::cout << "Read BW: " << bw_calc(read_bytes, rd_clk_count) << " GB/s"
<< std::endl;
std::cout << "Total BW: " << bw_calc(write_bytes + read_bytes, clk_count) << " GB/s\n"
<< std::endl;
cout << "Write bytes: " << std::dec << write_bytes
<< endl;
cout << "Read bytes: " << std::dec << read_bytes
<< endl;

if (wr_clk_count > 0)
cout << "Write BW: " << bw_calc(write_bytes, wr_clk_count) << " GB/s"
<< endl;
else
cout << "Write BW: N/A" << endl;

if (rd_clk_count > 0)
cout << "Read BW: " << bw_calc(read_bytes, rd_clk_count) << " GB/s"
<< endl;
else
cout << "Read BW: N/A" << endl;

if (clk_count > 0)
cout << "Total BW: " << bw_calc(write_bytes + read_bytes, clk_count) << " GB/s\n"
<< endl;
else
cout << "Total BW: N/A" << endl;
}

void tg_print_fail_info() {
Expand Down Expand Up @@ -269,6 +281,7 @@ class cxl_tg_test : public test_command {
}

tg_exe_->mem_speed_ = tg_exe_->read64(MEM_TG_CLK_FREQ);
std::cout << "Memory clock frequency (kHz) : " << tg_exe_->mem_speed_ << std::endl;
if (0 == tg_exe_->mem_speed_) {
tg_exe_->mem_speed_ = TG_FREQ;
std::cout << "Memory channel clock frequency unknown. Assuming "
Expand All @@ -295,24 +308,40 @@ class cxl_tg_test : public test_command {
tg_exe_->write32(TG_WRITE_REPEAT_COUNT, 0x1);
tg_exe_->write32(TG_READ_REPEAT_COUNT, 0x1);

tg_exe_->write32(TG_RW_GEN_IDLE_COUNT, 0x40);
tg_exe_->write32(TG_RW_GEN_LOOP_IDLE_COUNT, 0x200);
tg_exe_->write32(TG_RW_GEN_IDLE_COUNT, 0x1);
tg_exe_->write32(TG_RW_GEN_LOOP_IDLE_COUNT, 0x1);

tg_exe_->write32(TG_SEQ_START_ADDR_WR, 0x0000);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 0x04, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 8, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 12, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 16, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 20, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 0x08, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 0x0C, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 0x10, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_WR + 0x14, 0x0);

tg_exe_->write32(TG_ADDR_MODE_WR, 2);
tg_exe_->write32(TG_SEQ_ADDR_INCR, 0x3);
tg_exe_->write32(TG_SEQ_ADDR_INCR + 0x04, 0x0);
tg_exe_->write32(TG_ADDR_MODE_WR + 0x04 ,3 );
tg_exe_->write32(TG_ADDR_MODE_WR + 0x08 ,3 );
tg_exe_->write32(TG_ADDR_MODE_WR + 0x0C ,3 );
tg_exe_->write32(TG_ADDR_MODE_WR + 0x10 ,3 );
tg_exe_->write32(TG_ADDR_MODE_WR + 0x14 ,3 );

tg_exe_->write32(TG_SEQ_ADDR_INCR, 0x1);

tg_exe_->write32(TG_SEQ_START_ADDR_RD, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_RD + 0x04, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_RD + 0x08, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_RD + 0x0C, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_RD + 0x10, 0x0);
tg_exe_->write32(TG_SEQ_START_ADDR_RD + 0x14, 0x0);
tg_exe_->write32(TG_ADDR_MODE_RD, 2);

tg_exe_->write32(TG_ADDR_MODE_RD +0x04,3 );
tg_exe_->write32(TG_ADDR_MODE_RD +0x08,3 );
tg_exe_->write32(TG_ADDR_MODE_RD +0x0C,3 );
tg_exe_->write32(TG_ADDR_MODE_RD +0x10,3 );
tg_exe_->write32(TG_ADDR_MODE_RD +0x14,3 );

tg_exe_->write32(TG_USER_WORM_EN, 0);
tg_exe_->write32(TG_RETURN_TO_START_ADDR, 0);
uint32_t data_seed = 0x55555555;
tg_exe_->logger_->debug("configuring TG data seed");

Expand All @@ -322,10 +351,12 @@ class cxl_tg_test : public test_command {
tg_exe_->write32(TG_BYTEEN_SEED + i * 4, 0xffffffff);
tg_exe_->write32(TG_PPPG_SEL + i * 4, 0);
tg_exe_->write32(TG_BYTEEN_SEL + i * 4, 0);
tg_exe_->write32(0x1680 + i * 4, 1);
data_seed = ~data_seed;
}

for (uint32_t i = 0; i < 5; i++) {
tg_exe_->write32(0x1680 + i * 4, 0x1a);
}
return 0;
}

Expand Down

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