Merge cfb5f7d into b9dfc27

binaries/fpgainfo/fpgainfo.c

@@ -1,4 +1,4 @@
-// Copyright(c) 2018-2021, Intel Corporation
+// Copyright(c) 2018-2023, Intel Corporation
 //
 // Redistribution  and  use  in source  and  binary  forms,  with  or  without
 // modification, are permitted provided that the following conditions are met:
@@ -24,6 +24,10 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif // HAVE_CONFIG_H
+
 #define _GNU_SOURCE
 #include <string.h>
 
@@ -43,6 +47,18 @@ void fpgainfo_print_err(const char *s, fpga_result res)
 		fprintf(stderr, "Error %s: %s\n", s, fpgaErrStr(res));
 }
 
+STATIC const char *fpgainfo_interface_to_str(fpga_interface ifc)
+{
+	switch (ifc) {
+	case FPGA_IFC_DFL: return "DFL";
+	case FPGA_IFC_VFIO: return "VFIO";
+	case FPGA_IFC_SIM_DFL: return "Simulated DFL";
+	case FPGA_IFC_SIM_VFIO: return "Simulated VFIO";
+	case FPGA_IFC_UIO: return "UIO";
+	default: return "<unknown>";
+	}
+}
+
 void fpgainfo_print_common(const char *hdr, fpga_properties props)
 {
 	fpga_result res = FPGA_OK;
@@ -67,6 +83,7 @@ void fpgainfo_print_common(const char *hdr, fpga_properties props)
 	fpga_token par = NULL;
 	bool has_parent = true;
 	bool pr_valid = true;
+	fpga_interface interface = FPGA_IFC_DFL;
 
 	res = fpgaPropertiesGetObjectID(props, &object_id);
 	fpgainfo_print_err("reading object_id from properties", res);
@@ -101,6 +118,9 @@ void fpgainfo_print_common(const char *hdr, fpga_properties props)
 	res = fpgaPropertiesGetSubsystemDeviceID(props, &subdevice_id);
 	fpgainfo_print_err("reading subdevice_id from properties", res);
 
+	res = fpgaPropertiesGetInterface(props, &interface);
+	fpgainfo_print_err("reading interface from properties", res);
+
 	if (objtype != FPGA_DEVICE) {
 		res = fpgaPropertiesGetGUID(props, &port_guid);
 	}
@@ -163,6 +183,8 @@ void fpgainfo_print_common(const char *hdr, fpga_properties props)
 	}
 
 	printf("%s\n", hdr);
+	printf("%-32s : %s\n", "Interface",
+	       fpgainfo_interface_to_str(interface));
 	printf("%-32s : 0x%2" PRIX64 "\n", "Object Id", object_id);
 	printf("%-32s : %04X:%02X:%02X.%01X\n", "PCIe s:b:d.f", segment, bus,
 	       device, function);

cmake/config/config.h.in

@@ -249,5 +249,13 @@
 #define __OPAE_API__
 #endif
 
+#ifndef __VFIO_API__
+#define __VFIO_API__
+#endif
+
+#ifndef __UIO_API__
+#define __UIO_API__
+#endif
+
 #define SYSFS_PATH_MAX @SYSFS_PATH_MAX@
 #define DEV_PATH_MAX @DEV_PATH_MAX@

include/opae/types_enum.h

@@ -131,7 +131,10 @@ typedef enum {
 	FPGA_IFC_SIM_DFL,
 	/** FPGA_IFC_SIM_VFIO indicates that the plugin interface is the
 	 * AFU Simulation Environment simulating vfio-pci. */
-	FPGA_IFC_SIM_VFIO
+	FPGA_IFC_SIM_VFIO,
+	/** FPGA_IFC_UIO indicates that the plugin interface is the
+	 * uio-dfl driver. */
+	FPGA_IFC_UIO,
 } fpga_interface;
 
 /**

libraries/libopae-c/adapter.h

@@ -69,7 +69,7 @@ typedef struct _opae_api_adapter_table {
 				      uint64_t offset, uint32_t *value);
 
 	fpga_result (*fpgaWriteMMIO512)(fpga_handle handle, uint32_t mmio_num,
-				       uint64_t offset, void *value);
+				       uint64_t offset, const void *value);
 
 	fpga_result (*fpgaMapMMIO)(fpga_handle handle, uint32_t mmio_num,
 				   uint64_t **mmio_ptr);

libraries/libopae-c/api-shell.c

@@ -562,7 +562,7 @@ fpga_result __OPAE_API__ fpgaReadMMIO32(fpga_handle handle, uint32_t mmio_num,
 }
 
 fpga_result __OPAE_API__ fpgaWriteMMIO512(fpga_handle handle,
-	uint32_t mmio_num, uint64_t offset, void *value)
+	uint32_t mmio_num, uint64_t offset, const void *value)
 {
 	opae_wrapped_handle *wrapped_handle =
 		opae_validate_wrapped_handle(handle);

libraries/libopae-c/cfg-file.c

@@ -270,28 +270,46 @@ STATIC libopae_config_data default_libopae_config_table[] = {
 	{ 0x8086, 0xbcce, 0x8086,          0x138d,          "libxfpga.so",  "{}", 0 }, // D5005
 	{ 0x8086, 0xbcce, 0x8086,          0x138d,          "libopae-v.so", "{}", 0 }, // D5005
 	{ 0x8086, 0xbccf, 0x8086,          0x138d,          "libopae-v.so", "{}", 0 }, // D5005
+	{ 0x8086, 0xbcce, 0x8086,          0x138d,          "libopae-u.so", "{}", 0 }, // D5005
+	{ 0x8086, 0xbccf, 0x8086,          0x138d,          "libopae-u.so", "{}", 0 }, // D5005
+
 
 	{ 0x8086, 0x0b30, OPAE_VENDOR_ANY, OPAE_DEVICE_ANY, "libxfpga.so",  "{}", 0 }, // N3000
 	{ 0x8086, 0x0b31, OPAE_VENDOR_ANY, OPAE_DEVICE_ANY, "libxfpga.so",  "{}", 0 }, // N3000
 	{ 0x8086, 0xaf00, 0x8086,          0x0000,          "libxfpga.so",  "{}", 0 }, // OFS EA
 	{ 0x8086, 0xaf00, 0x8086,          0x0000,          "libopae-v.so", "{}", 0 }, // OFS EA
 	{ 0x8086, 0xaf01, 0x8086,          0x0000,          "libopae-v.so", "{}", 0 }, // OFS EA
+	{ 0x8086, 0xaf00, 0x8086,          0x0000,          "libopae-u.so", "{}", 0 }, // OFS EA
+	{ 0x8086, 0xaf01, 0x8086,          0x0000,          "libopae-u.so", "{}", 0 }, // OFS EA
+
 
 	{ 0x8086, 0xbcce, 0x8086,          0x0000,          "libxfpga.so",  "{}", 0 }, // OFS
 	{ 0x8086, 0xbcce, 0x8086,          0x0000,          "libopae-v.so", "{}", 0 }, // OFS
 	{ 0x8086, 0xbccf, 0x8086,          0x0000,          "libopae-v.so", "{}", 0 }, // OFS
+	{ 0x8086, 0xbcce, 0x8086,          0x0000,          "libopae-u.so", "{}", 0 }, // OFS
+	{ 0x8086, 0xbccf, 0x8086,          0x0000,          "libopae-u.so", "{}", 0 }, // OFS
+
 
 	{ 0x8086, 0xbcce, 0x8086,          0x1770,          "libxfpga.so",  "{}", 0 }, // N6000
 	{ 0x8086, 0xbcce, 0x8086,          0x1770,          "libopae-v.so", "{}", 0 }, // N6000
 	{ 0x8086, 0xbccf, 0x8086,          0x1770,          "libopae-v.so", "{}", 0 }, // N6000
+	{ 0x8086, 0xbcce, 0x8086,          0x1770,          "libopae-u.so", "{}", 0 }, // N6000
+	{ 0x8086, 0xbccf, 0x8086,          0x1770,          "libopae-u.so", "{}", 0 }, // N6000
+
 
 	{ 0x8086, 0xbcce, 0x8086,          0x1771,          "libxfpga.so",  "{}", 0 }, // N6001
 	{ 0x8086, 0xbcce, 0x8086,          0x1771,          "libopae-v.so", "{}", 0 }, // N6001
 	{ 0x8086, 0xbccf, 0x8086,          0x1771,          "libopae-v.so", "{}", 0 }, // N6001
+	{ 0x8086, 0xbcce, 0x8086,          0x1771,          "libopae-u.so", "{}", 0 }, // N6001
+	{ 0x8086, 0xbccf, 0x8086,          0x1771,          "libopae-u.so", "{}", 0 }, // N6001
+
 
 	{ 0x8086, 0xbcce, 0x8086,          0x17d4,          "libxfpga.so",  "{}", 0 }, // C6100
 	{ 0x8086, 0xbcce, 0x8086,          0x17d4,          "libopae-v.so", "{}", 0 }, // C6100
 	{ 0x8086, 0xbccf, 0x8086,          0x17d4,          "libopae-v.so", "{}", 0 }, // C6100
+	{ 0x8086, 0xbcce, 0x8086,          0x17d4,          "libopae-u.so", "{}", 0 }, // C6100
+	{ 0x8086, 0xbccf, 0x8086,          0x17d4,          "libopae-u.so", "{}", 0 }, // C6100
+
 
 	{      0,      0,      0,               0,          NULL,           NULL, 0 },
 };

libraries/libopaeuio/opaeuio.c

@@ -56,9 +56,13 @@
 	p;                                                \
 })
 
+#ifdef LIBOPAE_DEBUG
 #define ERR(format, ...)                               \
 fprintf(stderr, "%s:%u:%s() **ERROR** [%s] : " format, \
 	__SHORT_FILE__, __LINE__, __func__, strerror(errno), ##__VA_ARGS__)
+#else
+#define ERR(format, ...) do { } while (0)
+#endif
 
 // dfl_dev.xxx
 #define MAX_DFL_DEVICE 11

libraries/plugins/CMakeLists.txt

@@ -1,4 +1,4 @@
-## Copyright(c) 2017-2020, Intel Corporation
+## Copyright(c) 2017-2023, Intel Corporation
 ##
 ## Redistribution  and  use  in source  and  binary  forms,  with  or  without
 ## modification, are permitted provided that the following conditions are met:
@@ -35,3 +35,5 @@ if (OPAE_BUILD_PLUGIN_VFIO AND PLATFORM_SUPPORTS_VFIO)
             "Must enable 'OPAE_BUILD_LIBOPAEVFIO' to build vfio plugin")
     endif()
 endif()
+
+add_subdirectory(uio)

libraries/plugins/uio/CMakeLists.txt

@@ -0,0 +1,53 @@
+## Copyright(c) 2023, Intel Corporation
+##
+## Redistribution  and  use  in source  and  binary  forms,  with  or  without
+## modification, are permitted provided that the following conditions are met:
+##
+## * Redistributions of  source code  must retain the  above copyright notice,
+##   this list of conditions and the following disclaimer.
+## * Redistributions in binary form must reproduce the above copyright notice,
+##   this list of conditions and the following disclaimer in the documentation
+##   and/or other materials provided with the distribution.
+## * Neither the name  of Intel Corporation  nor the names of its contributors
+##   may be used to  endorse or promote  products derived  from this  software
+##   without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
+## IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
+## LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
+## CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
+## SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
+## INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
+## CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
+## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
+## POSSIBILITY OF SUCH DAMAGE.
+
+set(SRC
+  plugin.c
+  opae_uio.c
+  dfl.c
+  ${opae-test_ROOT}/framework/mock/opae_std.c
+)
+
+set(CMAKE_C_FLAGS "-std=gnu99 ${CMAKE_C_FLAGS}")
+
+opae_add_module_library(TARGET opae-u
+    SOURCE ${SRC}
+    LIBS
+        dl
+        m
+        ${CMAKE_THREAD_LIBS_INIT}
+        opae-c
+        opaeuio
+        ${json-c_LIBRARIES}
+        ${uuid_LIBRARIES}
+    COMPONENT uiolib
+)
+
+target_include_directories(opae-u
+    PRIVATE
+        ${OPAE_LIB_SOURCE}/libopae-c
+        ${uuid_INCLUDE}
+)