CP bug fixes from master (#1525)

* Squashed 'opae-libs/' changes from 426efe7..2aff141

2aff141 Fix spelling errors in public headers (#43)
36a40c7 Fix one-off bug in metrics. (#44)
c01a5bc Merge pull request #36 from OPAE/aravuri/fpga_dfl_header
6e08160 update GPLv2 license to BSD license for kenel ioctl files
78fe7e4 opae-lib: update fpga-dfl header file with latest changes

git-subtree-dir: opae-libs
git-subtree-split: 2aff141
(cherry picked from commit df0cc68)

* Merge commit 'df0cc68eb089c2a7da2a8ca0d6595cb59f9dc9a4'

* Squashed 'opae-libs/' changes from 2aff141..3743d9e

3743d9e Fix DOS line endings. (#45)

git-subtree-dir: opae-libs
git-subtree-split: 3743d9e

* Merge commit '0f4c78a92ee46f15e652fea9d46e6f94dac05094' into tswhison/pull_libs

* Merge pull request #1523 from OPAE/tswhison/pull_libs

Tswhison/pull libs

Co-authored-by: Tim Whisonant <tim.whisonant@intel.com>

opae-libs/include/opae/access.h

@@ -94,7 +94,7 @@ fpga_result fpgaClose(fpga_handle handle);
  *
  * @param[in]  handle   Handle to previously opened FPGA object
  * @returns             FPGA_OK on success. FPGA_INVALID_PARAM if handle does
- *                      not refer to an acquired resource or to a resoure that
+ *                      not refer to an acquired resource or to a resource that
  *                      cannot be reset. FPGA_EXCEPTION if an internal error
  *                      occurred while trying to access the handle or resetting
  *                      the resource.

opae-libs/include/opae/buffer.h

@@ -38,7 +38,7 @@
  * virtual address mappings of the CPU, so they can only access physical
  * addresses. To support this, the OPAE C library on Linux uses hugepages to
  * allocate large, contiguous pages of physical memory that can be shared with
- * an accalerator. It also supports sharing memory that has already been
+ * an accelerator. It also supports sharing memory that has already been
  * allocated by an application, as long as that memory satisfies the
  * requirements of being physically contigous and page-aligned.
  */

opae-libs/include/opae/metrics.h

@@ -118,7 +118,7 @@ fpga_result fpgaGetMetricsByName(fpga_handle handle,
  * @param[in] handle Handle to previously opened fpga resource
  * @param[inout] metrics_threshold pointer to array of metric thresholds
  * user allocates threshold array memory
- * Number of thresholds returns enumerated threholds if user pass
+ * Number of thresholds returns enumerated thresholds if user pass
  * NULL metrics_thresholds
  * @param[inout] num_thresholds number of thresholds
  *

opae-libs/include/opae/mmio.h

@@ -185,7 +185,7 @@ fpga_result fpgaMapMMIO(fpga_handle handle,
 /**
  * Unmap MMIO space
  *
- * This function will unmap a previously mapped MMIO space of the target opject,
+ * This function will unmap a previously mapped MMIO space of the target object,
  * rendering any pointers to it invalid.
  *
  * @note This call is only supported by hardware targets, not by ASE

opae-libs/include/opae/sysobject.h

@@ -178,7 +178,7 @@ fpga_result fpgaDestroyObject(fpga_object *obj);
  * If FPGA_OBJECT_SYNC is used then object will update its buffered copy before
  * retrieving the size.
  *
- * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of supplied paramters
+ * @return FPGA_OK on success. FPGA_INVALID_PARAM if any of supplied parameters
  * is invalid. FPGA_EXCEPTION if error occurred.
  */
 fpga_result fpgaObjectGetSize(fpga_object obj, uint32_t *value, int flags);

opae-libs/include/opae/types.h

@@ -40,7 +40,7 @@
  * variables of these types. In other words, before doing anything with a
  * variable of one of these opaque types, you need to first initialize them.
  *
- * The respective functions that initizalize opaque types are:
+ * The respective functions that initialize opaque types are:
  *
  *   * fpgaGetProperties() and fpgaCloneProperties() for `fpga_properties`
  *   * fpgaEnumerate() and fpgaCloneToken() for `fpga_token`

opae-libs/plugins/xfpga/fpga-dfl.h

@@ -1,15 +1,28 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Header File for FPGA DFL User API
- *
- * Copyright (C) 2017-2018 Intel Corporation, Inc.
- *
- * Authors:
- *   Kang Luwei <luwei.kang@intel.com>
- *   Zhang Yi <yi.z.zhang@intel.com>
- *   Wu Hao <hao.wu@intel.com>
- *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
- */
+// Copyright(c) 2017-2020, Intel Corporation
+//
+// Redistribution  and  use  in source  and  binary  forms,  with  or  without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of  source code  must retain the  above copyright notice,
+//   this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+// * Neither the name  of Intel Corporation  nor the names of its contributors
+//   may be used to  endorse or promote  products derived  from this  software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
+// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
+// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
+// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
+// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
+// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
+// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef _UAPI_LINUX_FPGA_DFL_H
 #define _UAPI_LINUX_FPGA_DFL_H
@@ -178,35 +191,20 @@ struct dfl_fpga_fme_port_pr {
 
 /**
  * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1,
- *					struct dfl_fpga_fme_port_release)
+ *						int port_id)
  *
  * Driver releases the port per Port ID provided by caller.
  * Return: 0 on success, -errno on failure.
  */
-struct dfl_fpga_fme_port_release {
-	/* Input */
-	__u32 argsz;		/* Structure length */
-	__u32 flags;		/* Zero for now */
-	__u32 port_id;
-};
-
-#define DFL_FPGA_FME_PORT_RELEASE	_IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 1)
+#define DFL_FPGA_FME_PORT_RELEASE   _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
 
 /**
  * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2,
- *					struct dfl_fpga_fme_port_assign)
+ *						int port_id)
  *
  * Driver assigns the port back per Port ID provided by caller.
  * Return: 0 on success, -errno on failure.
  */
-struct dfl_fpga_fme_port_assign {
-	/* Input */
-	__u32 argsz;		/* Structure length */
-	__u32 flags;		/* Zero for now */
-	__u32 port_id;
-};
-
-#define DFL_FPGA_FME_PORT_ASSIGN	_IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 2)
+#define DFL_FPGA_FME_PORT_ASSIGN     _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
 
 #endif /* _UAPI_LINUX_FPGA_DFL_H */
-

opae-libs/plugins/xfpga/intel-fpga.h

@@ -1,18 +1,29 @@
-/*
- * Header File for Intel FPGA User API
- *
- * Copyright 2016 Intel Corporation, Inc.
- *
- * Authors:
- *   Kang Luwei <luwei.kang@intel.com>
- *   Zhang Yi <yi.z.zhang@intel.com>
- *   Wu Hao <hao.wu@linux.intel.com>
- *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
- *
- * This work is licensed under the terms of the GNU GPL version 2. See
- * the COPYING file in the top-level directory.
- *
- */
+// Copyright(c) 2017-2020, Intel Corporation
+//
+// Redistribution  and  use  in source  and  binary  forms,  with  or  without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of  source code  must retain the  above copyright notice,
+//   this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+// * Neither the name  of Intel Corporation  nor the names of its contributors
+//   may be used to  endorse or promote  products derived  from this  software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
+// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
+// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
+// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
+// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
+// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
+// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
 
 #ifndef _UAPI_INTEL_FPGA_H
 #define _UAPI_INTEL_FPGA_H

opae-libs/plugins/xfpga/metrics/metrics_utils.c

@@ -132,7 +132,7 @@ fpga_result add_metric_vector(fpga_metric_vector *vector,
 	fpga_enum_metric->group_name[len] = '\0';
 
 	len = strnlen(group_sysfs, SYSFS_PATH_MAX - 1);
-	memcpy(fpga_enum_metric->group_sysfs, group_sysfs, len + 1);
+	memcpy(fpga_enum_metric->group_sysfs, group_sysfs, len);
 	fpga_enum_metric->group_sysfs[len] = '\0';
 
 	len = strnlen(metric_name, SYSFS_PATH_MAX - 1);

opae-libs/plugins/xfpga/opae_drv.c

@@ -395,24 +395,14 @@ fpga_result dfl_port_unmap(int fd, uint64_t io_addr)
 
 fpga_result dfl_fme_port_assign(int fd, uint32_t flags, uint32_t port_id)
 {
-	struct dfl_fpga_fme_port_assign assign = {
-		.argsz = sizeof(assign), .flags = 0, .port_id = port_id};
-	if (flags) {
-		OPAE_MSG(
-			"flags currently not supported in DFL_FPGA_FME_PORT_ASSIGN");
-	}
-	return opae_ioctl(fd, DFL_FPGA_FME_PORT_ASSIGN, &assign);
+	UNUSED_PARAM(flags);
+	return opae_ioctl(fd, DFL_FPGA_FME_PORT_ASSIGN, port_id);
 }
 
 fpga_result dfl_fme_port_release(int fd, uint32_t flags, uint32_t port_id)
 {
-	struct dfl_fpga_fme_port_assign assign = {
-		.argsz = sizeof(assign), .flags = 0, .port_id = port_id};
-	if (flags) {
-		OPAE_MSG(
-			"flags currently not supported in DFL_FPGA_FME_PORT_RELEASE");
-	}
-	return opae_ioctl(fd, DFL_FPGA_FME_PORT_RELEASE, &assign);
+	UNUSED_PARAM(flags);
+	return opae_ioctl(fd, DFL_FPGA_FME_PORT_RELEASE, port_id);
 }
 
 fpga_result dfl_fme_port_pr(int fd, uint32_t flags, uint32_t port_id,