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Fix: Remove latency iterations from write cache hit/miss scenario tests #3043

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merged 2 commits into from
Nov 16, 2023

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anandaravuri
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  • CXL host exerciser Remove latency iterations tests from write cache hit/miss scenario
  • Remove Bandwidth calculation and output in Read cache hit/miss scenario

   - CXL host exerciser Remove latency iterations tests from write cache hit/miss scenario
   - Remove Bandwidth calculation and output in Read cache hit/miss scenario

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
@anandaravuri anandaravuri requested a review from a team as a code owner November 14, 2023 19:40
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coveralls commented Nov 14, 2023

Pull Request Test Coverage Report for Build 6871282493

  • 0 of 28 (0.0%) changed or added relevant lines in 3 files are covered.
  • No unchanged relevant lines lost coverage.
  • Overall coverage increased (+0.3%) to 67.675%

Changes Missing Coverage Covered Lines Changed/Added Lines %
samples/cxl_host_exerciser/he_cache_test.h 0 2 0.0%
samples/cxl_host_exerciser/cxl_he_cmd.h 0 8 0.0%
samples/cxl_host_exerciser/cxl_he_cache_cmd.h 0 18 0.0%
Totals Coverage Status
Change from base Build 6871279370: 0.3%
Covered Lines: 15754
Relevant Lines: 23279

💛 - Coveralls

@anandaravuri anandaravuri merged commit 3a8b50e into master Nov 16, 2023
27 checks passed
@anandaravuri anandaravuri deleted the aravuri/fix_iter_bw branch November 16, 2023 18:03
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3 participants