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Feature:add loop count command line input to CXL host exerciser #3051

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merged 1 commit into from
Nov 28, 2023

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anandaravuri
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  • add loop count command line input and set read /write config
  • set FPGA / host read and write cache miss opcode to RD_LINE_I /WR_LINE_I

  - add loop count  command line input and set read /write config
  - set FPGA / host  read and write cache miss opcode to  RD_LINE_I /WR_LINE_I

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
@anandaravuri anandaravuri requested a review from a team as a code owner November 28, 2023 21:31
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Pull Request Test Coverage Report for Build 7024776232

  • 0 of 25 (0.0%) changed or added relevant lines in 2 files are covered.
  • 4 unchanged lines in 1 file lost coverage.
  • Overall coverage decreased (-0.06%) to 67.621%

Changes Missing Coverage Covered Lines Changed/Added Lines %
samples/cxl_host_exerciser/he_cache_test.h 0 2 0.0%
samples/cxl_host_exerciser/cxl_he_cache_cmd.h 0 23 0.0%
Files with Coverage Reduction New Missed Lines %
samples/cxl_host_exerciser/cxl_he_cache_cmd.h 4 0.0%
Totals Coverage Status
Change from base Build 6909983629: -0.06%
Covered Lines: 15755
Relevant Lines: 23299

💛 - Coveralls

@anandaravuri anandaravuri merged commit 7dcaef5 into master Nov 28, 2023
27 checks passed
@anandaravuri anandaravuri deleted the aravuri/fx_he_loop branch November 28, 2023 22:24
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3 participants