fix: set FPGA buffer read only for bias mode device bias.

[anandaravuri]

• Set Host and FPGA buffer map Writable for Host BIAS mode targeting Host address and Host BIAS mode targeting HDM (Device) address
• Set FPGA buffer map read-only for device BIAS mode targeting HDM (Device) address

CXL Driver IOCTL buffer map by default Read-only flag value is 0,
Set buffer map flag to DFL_CXL_BUFFER_MAP for Read/write buffers

struct dfl_cxl_cache_buffer_map {
__u32 argsz;
#define DFL_CXL_BUFFER_MAP_WRITABLE 1
__u32 flags;
__u64 user_addr;
__u64 length;
}

PR Title should start with one of the following tags: [Fix]/[Feature]/[Style]/[Update]

[Fix]- Bug Fix

[Feature]- for new feature

[Style]- Grammar or branding fix

[Update]-For an update to an existing feature

------------- Keep everything below this line -------------------------

Description

Describe the issue, update, change or fix and why

Collateral (docs, reports, design examples, case IDs):

• Document Update Required? (Specify FIM/AFU/Scripts)

Tests added:

Tests run:

[coveralls]

Pull Request Test Coverage Report for Build 7135138533

• 0 of 12 (0.0%) changed or added relevant lines in 2 files are covered.
• No unchanged relevant lines lost coverage.
• Overall coverage decreased (-0.03%) to 66.494%

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Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
samples/cxl_host_exerciser/cxl_he_cmd.h	0	1	0.0%
samples/cxl_host_exerciser/he_cache_test.h	0	11	0.0%

Totals
Change from base Build 7131768027:	-0.03%
Covered Lines:	15755
Relevant Lines:	23694

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💛 - Coveralls

[tswhison]

👍