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fix:set continuous mode bit for write hit/miss cases tests #3062

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merged 2 commits into from
Dec 18, 2023

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anandaravuri
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@anandaravuri anandaravuri commented Dec 15, 2023

CXL HE write hit/miss cases, sets continuous mode bit in rd_cfg instead of wr_cfg.
set continuous mode bit write hit/miss case tests.

Forced stop control register ResetL bit is low causes timeout failures
set ResetL too high for forced stop

@tswhison
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Could you provide some description in the commit message indicating why the change is required?

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Can add to the commit message as to why this needs to be done and why the change involving removing setting he_rw_cfg_.continuous_mode_enable?

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coveralls commented Dec 15, 2023

Pull Request Test Coverage Report for Build 7227997314

  • 0 of 5 (0.0%) changed or added relevant lines in 1 file are covered.
  • 1 unchanged line in 1 file lost coverage.
  • Overall coverage decreased (-0.003%) to 66.565%

Changes Missing Coverage Covered Lines Changed/Added Lines %
samples/cxl_host_exerciser/cxl_he_cache_cmd.h 0 5 0.0%
Files with Coverage Reduction New Missed Lines %
samples/cxl_host_exerciser/cxl_he_cache_cmd.h 1 0.0%
Totals Coverage Status
Change from base Build 7227971434: -0.003%
Covered Lines: 15756
Relevant Lines: 23670

💛 - Coveralls

@anandaravuri
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Can add to the commit message as to why this needs to be done and why the change involving removing setting he_rw_cfg_.continuous_mode_enable?

Ananda: updated commit meassge with comments

 CXL HE write hit/miss cases, sets continuous mode bit in rd_cfg instead of wr_cfg.
 set continuous mode bit write hit/miss case tests.

 Forced stop  control register ResetL bit is low causes timeout failures
 set ResetL too high for forced stop

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
@anandaravuri anandaravuri merged commit 6c1c4bd into master Dec 18, 2023
27 checks passed
@anandaravuri anandaravuri deleted the aravuri/fix_contmode branch December 18, 2023 18:31
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5 participants