/
board.c
3302 lines (2919 loc) · 93.2 KB
/
board.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <devices.h>
#include <version.h>
#include <net.h>
#include <environment.h>
#include <asm/mipsregs.h>
#include <rt_mmap.h>
#include <spi_api.h>
#include <nand_api.h>
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
#define SDRAM_CFG1_REG RALINK_SYSCTL_BASE + 0x0304
int modifies= 0;
#ifdef DEBUG
#define DATE "05/25/2006"
#define VERSION "v0.00e04"
#endif
#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
(CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
defined(CFG_ENV_IS_IN_NVRAM)
#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
#else
#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
#endif
#define ARGV_LEN 128
#if defined (RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
static int watchdog_reset();
#endif
extern int timer_init(void);
extern void rt2880_eth_halt(struct eth_device* dev);
extern void setup_internal_gsw(void);
extern void setup_external_gsw(void);
//extern void pci_init(void);
extern int incaip_set_cpuclk(void);
extern int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int flash_sect_protect (int p, ulong addr_first, ulong addr_last);
int flash_sect_erase (ulong addr_first, ulong addr_last);
int get_addr_boundary (ulong *addr);
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void input_value(u8 *str);
#if defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD) || \
defined (MT7620_ASIC_BOARD) || defined (MT7620_FPGA_BOARD)
extern void rt_gsw_init(void);
#elif defined (RT6855A_ASIC_BOARD) || defined (RT6855A_FPGA_BOARD)
extern void rt6855A_gsw_init(void);
#elif defined (RT3883_ASIC_BOARD) && defined (MAC_TO_MT7530_MODE)
extern void rt3883_gsw_init(void);
#else
extern void rt305x_esw_init(void);
#endif
extern void LANWANPartition(void);
extern struct eth_device* rt2880_pdev;
extern ulong uboot_end_data;
extern ulong uboot_end;
#if defined (RALINK_USB ) || defined (MTK_USB)
extern int usb_stor_curr_dev;
#endif
ulong monitor_flash_len;
const char version_string[] =
U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
extern ulong load_addr; /* Default Load Address */
unsigned long mips_cpu_feq;
unsigned long mips_bus_feq;
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
static ulong mem_malloc_start;
static ulong mem_malloc_end;
static ulong mem_malloc_brk;
static char file_name_space[ARGV_LEN];
#define read_32bit_cp0_register_with_select1(source) \
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
"mfc0\t%0,"STR(source)",1\n\t" \
".set\tpop" \
: "=r" (__res)); \
__res;})
//added by mango
void gpio_init(void);
void led_on(void);
void led_off(void);
// Added by zh@onion.io
int detect_rst(void); // rename wps button to rst
void gpio_test(int vtest);
void write_macAddress(void); // Added by jeffzhou@onion.io
void set_gpio_led(int vreg,int vgpio) ;//jeff
static void Init_System_Mode(void)
{
u32 reg;
#ifdef ASIC_BOARD
u8 clk_sel;
#endif
#if defined(RT5350_ASIC_BOARD)
u8 clk_sel2;
#endif
reg = RALINK_REG(RT2880_SYSCFG_REG);
/*
* CPU_CLK_SEL (bit 21:20)
*/
#ifdef RT2880_FPGA_BOARD
mips_cpu_feq = 25 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || defined (RT5350_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/3;
#elif defined (RT6855A_FPGA_BOARD)
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/2;
#elif defined (RT3883_FPGA_BOARD)
mips_cpu_feq = 40 * 1000 *1000;
mips_bus_feq = mips_cpu_feq;
#elif defined (RT6855_FPGA_BOARD) || defined (MT7620_FPGA_BOARD) || defined (MT7628_FPGA_BOARD)
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/4;
#elif defined (MT7621_FPGA_BOARD)
mips_cpu_feq = 50 * 1000 *1000;
mips_bus_feq = mips_cpu_feq/4;
#elif defined (RT2883_ASIC_BOARD)
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (380*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
case 2:
mips_cpu_feq = (420*1000*1000);
break;
case 3:
mips_cpu_feq = (430*1000*1000);
break;
}
mips_bus_feq = mips_cpu_feq/2;
#elif defined(RT3052_ASIC_BOARD)
#if defined(RT3350_ASIC_BOARD)
//MA10 is floating
mips_cpu_feq = (320*1000*1000);
#else
clk_sel = (reg>>18) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (320*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
}
#endif
mips_bus_feq = mips_cpu_feq / 3;
#elif defined(RT3352_ASIC_BOARD)
clk_sel = (reg>>8) & 0x01;
switch(clk_sel) {
case 0:
mips_cpu_feq = (384*1000*1000);
break;
case 1:
mips_cpu_feq = (400*1000*1000);
break;
}
mips_bus_feq = (133*1000*1000);
#elif defined(RT5350_ASIC_BOARD)
clk_sel2 = (reg>>10) & 0x01;
clk_sel = ((reg>>8) & 0x01) + (clk_sel2 * 2);
switch(clk_sel) {
case 0:
mips_cpu_feq = (360*1000*1000);
mips_bus_feq = (120*1000*1000);
break;
case 1:
//reserved
break;
case 2:
mips_cpu_feq = (320*1000*1000);
mips_bus_feq = (80*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
mips_bus_feq = (100*1000*1000);
break;
}
#elif defined(RT6855_ASIC_BOARD)
mips_cpu_feq = (400*1000*1000);
mips_bus_feq = (133*1000*1000);
#elif defined (RT6855A_ASIC_BOARD)
/* FPGA is 25/32Mhz
* ASIC RT6856/RT63368: DDR(0): 233.33, DDR(1): 175, SDR: 140
* RT6855/RT6855A: DDR(0): 166.67, DDR(1): 125, SDR: 140 */
reg = RALINK_REG(RT2880_SYSCFG_REG);
if ((reg & (1 << 25)) == 0) { /* SDR */
if ((reg & (1 << 9)) != 0)
mips_cpu_feq = (560*1000*1000);
else {
if ((reg & (1 << 26)) != 0)
mips_cpu_feq = (560*1000*1000);
else
mips_cpu_feq = (420*1000*1000);
}
mips_bus_feq = (140*1000*1000);
} else { /* DDR */
if ((reg & (1 << 9)) != 0) {
mips_cpu_feq = (700*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (175*1000*1000);
else
mips_bus_feq = 233333333;
} else {
mips_cpu_feq = (500*1000*1000);
if ((reg & (1 << 26)) != 0)
mips_bus_feq = (125*1000*1000);
else
mips_bus_feq = 166666667;
}
}
#elif defined(MT7620_ASIC_BOARD)
reg = RALINK_REG(RALINK_CPLLCFG1_REG);
if( reg & ((0x1UL) << 24) ){
mips_cpu_feq = (480*1000*1000); /* from BBP PLL */
}else{
reg = RALINK_REG(RALINK_CPLLCFG0_REG);
if(!(reg & CPLL_SW_CONFIG)){
mips_cpu_feq = (600*1000*1000); /* from CPU PLL */
}else{
/* read CPLL_CFG0 to determine real CPU clock */
int mult_ratio = (reg & CPLL_MULT_RATIO) >> CPLL_MULT_RATIO_SHIFT;
int div_ratio = (reg & CPLL_DIV_RATIO) >> CPLL_DIV_RATIO_SHIFT;
mult_ratio += 24; /* begin from 24 */
if(div_ratio == 0) /* define from datasheet */
div_ratio = 2;
else if(div_ratio == 1)
div_ratio = 3;
else if(div_ratio == 2)
div_ratio = 4;
else if(div_ratio == 3)
div_ratio = 8;
mips_cpu_feq = ((BASE_CLOCK * mult_ratio ) / div_ratio) * 1000 * 1000;
}
}
reg = (RALINK_REG(RT2880_SYSCFG_REG)) >> 4 & 0x3;
if(reg == 0x0){ /* SDR (MT7620 E1) */
mips_bus_feq = mips_cpu_feq/4;
}else if(reg == 0x1 || reg == 0x2 ){ /* DDR1 & DDR2 */
mips_bus_feq = mips_cpu_feq/3;
}else{ /* SDR (MT7620 E2) */
mips_bus_feq = mips_cpu_feq/5;
}
#elif defined (MT7628_ASIC_BOARD)
reg = RALINK_REG(RALINK_CLKCFG0_REG);
if (reg & (0x1<<1)) {
mips_cpu_feq = (480*1000*1000)/CPU_FRAC_DIV;
}else if (reg & 0x1) {
mips_cpu_feq = ((RALINK_REG(RALINK_SYSCTL_BASE+0x10)>>6)&0x1) ? (40*1000*1000)/CPU_FRAC_DIV \
: (25*1000*1000)/CPU_FRAC_DIV;
}else {
mips_cpu_feq = (575*1000*1000)/CPU_FRAC_DIV;
}
mips_bus_feq = mips_cpu_feq/3;
#elif defined(MT7621_ASIC_BOARD)
reg = RALINK_REG(RALINK_SYSCTL_BASE + 0x2C);
if( reg & ((0x1UL) << 30)) {
reg = RALINK_REG(RALINK_MEMCTRL_BASE + 0x648);
mips_cpu_feq = (((reg >> 4) & 0x7F) + 1) * 1000 * 1000;
reg = RALINK_REG(RALINK_SYSCTL_BASE + 0x10);
reg = (reg >> 6) & 0x7;
if(reg >= 6) { //25Mhz Xtal
mips_cpu_feq = mips_cpu_feq * 25;
} else if (reg >=3) { //40Mhz Xtal
mips_cpu_feq = mips_cpu_feq * 20;
} else { //20Mhz Xtal
/* TODO */
}
}else {
reg = RALINK_REG(RALINK_SYSCTL_BASE + 0x44);
mips_cpu_feq = (500 * (reg & 0x1F) / ((reg >> 8) & 0x1F)) * 1000 * 1000;
}
mips_bus_feq = mips_cpu_feq/4;
#elif defined (RT3883_ASIC_BOARD)
clk_sel = (reg>>8) & 0x03;
switch(clk_sel) {
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (384*1000*1000);
break;
case 2:
mips_cpu_feq = (480*1000*1000);
break;
case 3:
mips_cpu_feq = (500*1000*1000);
break;
}
#if defined (CFG_ENV_IS_IN_SPI)
if ((reg>>17) & 0x1) { //DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
}
else {
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
}
#elif defined ON_BOARD_SDR
switch(clk_sel) {
case 0:
mips_bus_feq = (83*1000*1000);
break;
case 1:
mips_bus_feq = (96*1000*1000);
break;
case 2:
mips_bus_feq = (120*1000*1000);
break;
case 3:
mips_bus_feq = (125*1000*1000);
break;
}
#elif defined ON_BOARD_DDR2
switch(clk_sel) {
case 0:
mips_bus_feq = (125*1000*1000);
break;
case 1:
mips_bus_feq = (128*1000*1000);
break;
case 2:
mips_bus_feq = (160*1000*1000);
break;
case 3:
mips_bus_feq = (166*1000*1000);
break;
}
#else
#error undef SDR or DDR
#endif
#else /* RT2880 ASIC version */
clk_sel = (reg>>20) & 0x03;
switch(clk_sel) {
#ifdef RT2880_MP
case 0:
mips_cpu_feq = (250*1000*1000);
break;
case 1:
mips_cpu_feq = (266*1000*1000);
break;
case 2:
mips_cpu_feq = (280*1000*1000);
break;
case 3:
mips_cpu_feq = (300*1000*1000);
break;
#else
case 0:
mips_cpu_feq = (233*1000*1000);
break;
case 1:
mips_cpu_feq = (250*1000*1000);
break;
case 2:
mips_cpu_feq = (266*1000*1000);
break;
case 3:
mips_cpu_feq = (280*1000*1000);
break;
#endif
}
mips_bus_feq = mips_cpu_feq/2;
#endif
//RALINK_REG(RT2880_SYSCFG_REG) = reg;
/* in general, the spec define 8192 refresh cycles/64ms
* 64ms/8192 = 7.8us
* 7.8us * 106.7Mhz(SDRAM clock) = 832
* the value of refresh cycle shall smaller than 832.
* so we config it at 0x300 (suggested by ASIC)
*/
#if defined(ON_BOARD_SDR) && defined(ON_BOARD_256M_DRAM_COMPONENT) && (!defined(MT7620_ASIC_BOARD))
{
u32 tREF;
tREF = RALINK_REG(SDRAM_CFG1_REG);
tREF &= 0xffff0000;
#if defined(ASIC_BOARD)
tREF |= 0x00000300;
#elif defined(FPGA_BOARD)
tREF |= 0x000004B;
#else
#error "not exist"
#endif
RALINK_REG(SDRAM_CFG1_REG) = tREF;
}
#endif
}
/*
* The Malloc area is immediately below the monitor copy in DRAM
*/
static void mem_malloc_init (void)
{
ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
mem_malloc_end = dest_addr;
mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_brk = mem_malloc_start;
memset ((void *) mem_malloc_start,
0,
mem_malloc_end - mem_malloc_start);
}
void *sbrk (ptrdiff_t increment)
{
ulong old = mem_malloc_brk;
ulong new = old + increment;
if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
return (NULL);
}
mem_malloc_brk = new;
return ((void *) old);
}
static int init_func_ram (void)
{
#ifdef CONFIG_BOARD_TYPES
int board_type = gd->board_type;
#else
int board_type = 0; /* use dummy arg */
#endif
puts ("DRAM: ");
/*init dram config*/
#ifdef RALINK_DDR_OPTIMIZATION
#ifdef ON_BOARD_DDR2
/*optimize ddr parameter*/
{
u32 tDDR;
tDDR = RALINK_REG(DDR_CFG0_REG);
tDDR &= 0xf0780000;
tDDR |= RAS_VALUE << RAS_OFFSET;
tDDR |= TRFC_VALUE << TRFC_OFFSET;
tDDR |= TRFI_VALUE << TRFI_OFFSET;
RALINK_REG(DDR_CFG0_REG) = tDDR;
}
#endif
#endif
if ((gd->ram_size = initdram (board_type)) > 0) {
print_size (gd->ram_size, "\n");
return (0);
}
puts ("*** failed ***\n");
return (1);
}
static int display_banner(void)
{
printf ("\n\n ____ _ ____\n"
" / __ \\___ (_)__ ___ / __ \\__ _ ___ ___ ____ _\n"
" / /_/ / _ \\/ / _ \\/ _ \\ / /_/ / ' \\/ -_) _ `/ _ `/\n"
" \\____/_//_/_/\\___/_//_/ \\____/_/_/_/\\__/\\_, /\\_,_/\n"
" W H A T W I L L Y O U I N V E N T ? /___/\"\n\n");
return (0);
}
/*
static void display_flash_config(ulong size)
{
puts ("Flash: ");
print_size (size, "\n");
}
*/
static int init_baudrate (void)
{
//uchar tmp[64]; /* long enough for environment variables */
//int i = getenv_r ("baudrate", tmp, sizeof (tmp));
//kaiker
gd->baudrate = CONFIG_BAUDRATE;
/*
gd->baudrate = (i > 0)
? (int) simple_strtoul (tmp, NULL, 10)
: CONFIG_BAUDRATE;
*/
return (0);
}
/*
* Breath some life into the board...
*
* The first part of initialization is running from Flash memory;
* its main purpose is to initialize the RAM so that we
* can relocate the monitor code to RAM.
*/
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
* requirements are just _too_ different. To get rid of the resulting
* mess of board dependend #ifdef'ed code we now make the whole
* initialization sequence configurable to the user.
*
* The requirements for any new initalization function is simple: it
* receives a pointer to the "global data" structure as it's only
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
#if 0
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
timer_init,
env_init, /* initialize environment */
init_baudrate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f,
display_banner, /* say that we are here */
checkboard,
init_func_ram,
NULL,
};
#endif
//
void board_init_f(ulong bootflag)
{
gd_t gd_data, *id;
bd_t *bd;
//init_fnc_t **init_fnc_ptr;
ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE;
ulong *s;
u32 value;
u32 fdiv = 0, step = 0, frac = 0, i;
#if defined RT6855_FPGA_BOARD || defined RT6855_ASIC_BOARD || \
defined MT7620_FPGA_BOARD || defined MT7620_ASIC_BOARD
value = le32_to_cpu(*(volatile u_long *)(RALINK_SPI_BASE + 0x10));
value &= ~(0x7);
value |= 0x2;
*(volatile u_long *)(RALINK_SPI_BASE + 0x10) = cpu_to_le32(value);
#elif defined MT7621_FPGA_BOARD || defined MT7628_FPGA_BOARD
value = le32_to_cpu(*(volatile u_long *)(RALINK_SPI_BASE + 0x3c));
value &= ~(0xFFF);
*(volatile u_long *)(RALINK_SPI_BASE + 0x3c) = cpu_to_le32(value);
#elif defined MT7621_ASIC_BOARD
value = le32_to_cpu(*(volatile u_long *)(RALINK_SPI_BASE + 0x3c));
value &= ~(0xFFF);
value |= 5; //work-around 3-wire SPI issue (3 for RFB, 5 for EVB)
*(volatile u_long *)(RALINK_SPI_BASE + 0x3c) = cpu_to_le32(value);
#elif defined MT7628_ASIC_BOARD
value = le32_to_cpu(*(volatile u_long *)(RALINK_SPI_BASE + 0x3c));
value &= ~(0xFFF);
value |= 8;
*(volatile u_long *)(RALINK_SPI_BASE + 0x3c) = cpu_to_le32(value);
#endif
#if defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD)
/* Adjust CPU Freq from 60Mhz to 600Mhz(or CPLL freq stored from EE) */
value = RALINK_REG(RT2880_SYSCLKCFG_REG);
fdiv = ((value>>8)&0x1F);
step = (unsigned long)(value&0x1F);
while(step < fdiv) {
value = RALINK_REG(RT2880_SYSCLKCFG_REG);
step = (unsigned long)(value&0x1F) + 1;
value &= ~(0x1F);
value |= (step&0x1F);
RALINK_REG(RT2880_SYSCLKCFG_REG) = value;
udelay(10);
};
#elif defined(MT7628_ASIC_BOARD)
value = RALINK_REG(RALINK_DYN_CFG0_REG);
fdiv = (unsigned long)((value>>8)&0x0F);
if ((CPU_FRAC_DIV < 1) || (CPU_FRAC_DIV > 10))
frac = (unsigned long)(value&0x0F);
else
frac = CPU_FRAC_DIV;
i = 0;
while(frac < fdiv) {
value = RALINK_REG(RALINK_DYN_CFG0_REG);
fdiv = ((value>>8)&0x0F);
fdiv--;
value &= ~(0x0F<<8);
value |= (fdiv<<8);
RALINK_REG(RALINK_DYN_CFG0_REG) = value;
udelay(500);
i++;
value = RALINK_REG(RALINK_DYN_CFG0_REG);
fdiv = ((value>>8)&0x0F);
//frac = (unsigned long)(value&0x0F);
}
#elif defined (MT7621_ASIC_BOARD)
#if (MT7621_CPU_FREQUENCY!=50)
value = RALINK_REG(RALINK_CUR_CLK_STS_REG);
fdiv = ((value>>8)&0x1F);
frac = (unsigned long)(value&0x1F);
i = 0;
while(frac < fdiv) {
value = RALINK_REG(RALINK_DYN_CFG0_REG);
fdiv = ((value>>8)&0x0F);
fdiv--;
value &= ~(0x0F<<8);
value |= (fdiv<<8);
RALINK_REG(RALINK_DYN_CFG0_REG) = value;
udelay(500);
i++;
value = RALINK_REG(RALINK_CUR_CLK_STS_REG);
fdiv = ((value>>8)&0x1F);
frac = (unsigned long)(value&0x1F);
}
#endif
#if ((MT7621_CPU_FREQUENCY!=50) && (MT7621_CPU_FREQUENCY!=500))
//change CPLL from GPLL to MEMPLL
value = RALINK_REG(RALINK_CLKCFG0_REG);
value &= ~(0x3<<30);
value |= (0x1<<30);
RALINK_REG(RALINK_CLKCFG0_REG) = value;
#endif
#endif
#ifdef CONFIG_PURPLE
void copy_code (ulong);
#endif
//*pio_mode = 0xFFFF;
/* Pointer is writable since we allocated a register for it.
*/
gd = &gd_data;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset ((void *)gd, 0, sizeof (gd_t));
#if defined (RT6855A_ASIC_BOARD) || defined(RT6855A_FPGA_BOARD)
watchdog_reset();
#endif
timer_init();
env_init(); /* initialize environment */
init_baudrate(); /* initialze baudrate settings */
serial_init(); /* serial communications setup */
console_init_f();
display_banner(); /* say that we are here */
checkboard();
init_func_ram();
/* reset Frame engine */
value = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034));
udelay(100);
#if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD)
value |= (1 << 18);
#elif defined (MT7621_FPGA_BOARD) || defined (MT7621_ASIC_BOARD)
/* nothing */
//value |= (1<<26 | 1<<25 | 1<<24); /* PCIE de-assert for E3 */
#else
//2880 -> 3052 reset Frame Engine from 18 to 21
value |= (1 << 21);
#endif
*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(value);
#if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD)
value &= ~(1 << 18);
#elif defined (MT7621_FPGA_BOARD) || defined (MT7621_ASIC_BOARD)
/* nothing */
#else
value &= ~(1 << 21);
#endif
*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(value);
udelay(200);
#if 0
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
#endif
#ifdef DEBUG
debug("rt2880 uboot %s %s\n", VERSION, DATE);
#endif
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*/
addr = CFG_SDRAM_BASE + gd->ram_size;
/* We can reserve some RAM "on top" here.
*/
#ifdef DEBUG
debug ("SERIAL_CLOCK_DIVISOR =%d \n", SERIAL_CLOCK_DIVISOR);
debug ("kaiker,,CONFIG_BAUDRATE =%d \n", CONFIG_BAUDRATE);
debug ("SDRAM SIZE:%08X\n",gd->ram_size);
#endif
/* round down to next 4 kB limit.
*/
addr &= ~(4096 - 1);
#ifdef DEBUG
debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
#endif
/* Reserve memory for U-Boot code, data & bss
* round down to next 16 kB limit
*/
addr -= len;
addr &= ~(16 * 1024 - 1);
#ifdef DEBUG
debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
#endif
/* Reserve memory for malloc() arena.
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
#ifdef DEBUG
debug ("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, addr_sp);
#endif
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
addr_sp -= sizeof(bd_t);
bd = (bd_t *)addr_sp;
gd->bd = bd;
#ifdef DEBUG
debug ("Reserving %d Bytes for Board Info at: %08lx\n",
sizeof(bd_t), addr_sp);
#endif
addr_sp -= sizeof(gd_t);
id = (gd_t *)addr_sp;
#ifdef DEBUG
debug ("Reserving %d Bytes for Global Data at: %08lx\n",
sizeof (gd_t), addr_sp);
#endif
/* Reserve memory for boot params.
*/
addr_sp -= CFG_BOOTPARAMS_LEN;
bd->bi_boot_params = addr_sp;
#ifdef DEBUG
debug ("Reserving %dk for boot params() at: %08lx\n",
CFG_BOOTPARAMS_LEN >> 10, addr_sp);
#endif
/*
* Finally, we set up a new (bigger) stack.
*
* Leave some safety gap for SP, force alignment on 16 byte boundary
* Clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
s = (ulong *)addr_sp;
*s-- = 0;
*s-- = 0;
addr_sp = (ulong)s;
#ifdef DEBUG
debug ("Stack Pointer at: %08lx\n", addr_sp);
#endif
/*
* Save local variables to board info struct
*/
bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
memcpy (id, (void *)gd, sizeof (gd_t));
/* On the purple board we copy the code in a special way
* in order to solve flash problems
*/
#ifdef CONFIG_PURPLE
copy_code(addr);
#endif
#if defined(CFG_RUN_CODE_IN_RAM)
/*
* tricky: relocate code to original TEXT_BASE
* for ICE souce level debuggind mode
*/
debug ("relocate_code Pointer at: %08lx\n", addr);
relocate_code (addr_sp, id, /*TEXT_BASE*/ addr);
#else
debug ("relocate_code Pointer at: %08lx\n", addr);
relocate_code (addr_sp, id, addr);
#endif
/* NOTREACHED - relocate_code() does not return */
}
#define TEMP_MAINTENANCE
#define SEL_BOOT_FLASH -1
#define SEL_WEB_MODE 0
#define SEL_ENTER_CLI 1
#define SEL_LOAD_LINUX_USB 2
#define SEL_LOAD_LINUX_SDRAM 3
#define SEL_LOAD_LINUX_WRITE_FLASH_BY_SERIAL 4
#define SEL_LOAD_LINUX_WRITE_FLASH 5
#define SEL_LOAD_BOOT_USB 6
#define SEL_LOAD_BOOT_SDRAM 7
#define SEL_LOAD_BOOT_WRITE_FLASH_BY_SERIAL 8
#define SEL_LOAD_BOOT_WRITE_FLASH 9
//#define SEL_TEST_LEDS x
void OperationSelect(void)
{
printf("\nPlease select option: \n");
//printf(" %d: Enter led testing mode.\n", SEL_TEST_LEDS);
// zh@onion.io
// update boot menu format
printf(" [ Enter ]: Boot Omega2.\n");
// zh@onion.io
#ifdef ONION_WEB_FLASH
printf(" [ %d ]: Start Web recovery mode.\n", SEL_WEB_MODE);
#endif //ONION_WEB_FLASH
#ifdef RALINK_CMDLINE
printf(" [ %d ]: Start command line mode.\n", SEL_ENTER_CLI);
#endif // RALINK_CMDLINE //
#ifdef ONION_USB_FLASH
printf(" [ %d ]: Flash firmware from USB storage. \n", SEL_LOAD_LINUX_USB);
#endif //ONION_USB_FLASH
#ifdef ONION_TFTP_FLASH_SDRAM
printf(" [ %d ]: Flash firmware to SDRAM via TFTP. \n", SEL_LOAD_LINUX_SDRAM);
#endif // ONION_TFTP_FLASH
#ifdef RALINK_UPGRADE_BY_SERIAL
printf(" [ %d ]: Flash firmware via Serial. \n", SEL_LOAD_LINUX_WRITE_FLASH_BY_SERIAL);
#endif // RALINK_UPGRADE_BY_SERIAL //
#ifdef ONION_TFTP_FLASH
printf(" [ %d ]: Flash firmware via TFTP. \n", SEL_LOAD_LINUX_WRITE_FLASH);
#endif // ONION_TFTP_FLASH
// #ifdef ONION_USB_FLASH
// printf(" [ %d ]: Flash boot loader code from USB. \n", SEL_LOAD_BOOT_USB);
// #endif
#ifdef ONION_TFTP_FLASH_SDRAM
printf(" [ %d ]: Flash boot loader code then write to SDRAM via TFTP. \n", SEL_LOAD_BOOT_SDRAM);
#endif
#ifdef RALINK_UPGRADE_BY_SERIAL
printf(" [ %d ]: Flash boot loader via Serial. \n", SEL_LOAD_BOOT_WRITE_FLASH_BY_SERIAL);
#endif // RALINK_UPGRADE_BY_SERIAL //
#ifdef ONION_TFTP_FLASH
printf(" [ %d ]: Flash boot loader via TFTP. \n", SEL_LOAD_BOOT_WRITE_FLASH);
#endif // ONION_TFTP_FLASH
}
int tftp_config(int type, char *argv[])
{
char *s;
char default_file[ARGV_LEN], file[ARGV_LEN], devip[ARGV_LEN], srvip[ARGV_LEN], default_ip[ARGV_LEN];
printf(" Please Input new ones /or Ctrl-C to discard\n");
memset(default_file, 0, ARGV_LEN);
memset(file, 0, ARGV_LEN);
memset(devip, 0, ARGV_LEN);
memset(srvip, 0, ARGV_LEN);
memset(default_ip, 0, ARGV_LEN);
printf("\tInput device IP ");
s = getenv("ipaddr");
memcpy(devip, s, strlen(s));
memcpy(default_ip, s, strlen(s));
printf("(%s) ", devip);
input_value(devip);
setenv("ipaddr", devip);
if (strcmp(default_ip, devip) != 0)
modifies++;
printf("\tInput server IP ");
s = getenv("serverip");
memcpy(srvip, s, strlen(s));
memset(default_ip, 0, ARGV_LEN);
memcpy(default_ip, s, strlen(s));
printf("(%s) ", srvip);
input_value(srvip);
setenv("serverip", srvip);
if (strcmp(default_ip, srvip) != 0)
modifies++;
if(type == SEL_LOAD_BOOT_SDRAM
|| type == SEL_LOAD_BOOT_WRITE_FLASH
#ifdef RALINK_UPGRADE_BY_SERIAL
|| type == SEL_LOAD_BOOT_WRITE_FLASH_BY_SERIAL
#endif
) {
if(type == SEL_LOAD_BOOT_SDRAM)
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)
argv[1] = "0x8a200000";
#else
argv[1] = "0x80200000";
#endif
else
#if defined (RT2880_ASIC_BOARD) || defined (RT2880_FPGA_BOARD)