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Enable cache, IPI, exception and shared-memory operations on Versal A72 for Libmetal. Additionally, as the code for A72 and A53 is almost identical, move the common code to generic/xlnx_common/zynqmp_aarch64 and differentiate the slight differences with macro checks. Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com> Acked-by: tanmay.shah@xilinx.com
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collect (PROJECT_LIB_HEADERS sys.h) | ||
collect (PROJECT_LIB_SOURCES sys.c) |
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/* | ||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved. | ||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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/* | ||
* @file generic/xlnx_common/zynqmp_aarch64/sys.c | ||
* @brief machine specific system primitives implementation. | ||
*/ | ||
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#include <metal/compiler.h> | ||
#include <metal/io.h> | ||
#include <metal/sys.h> | ||
#include <stdint.h> | ||
#include "xil_cache.h" | ||
#include "xil_exception.h" | ||
#include "xil_mmu.h" | ||
#include "xscugic.h" | ||
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#if defined(versal) | ||
#include "xcpu_cortexa72.h" | ||
#else | ||
#include "xreg_cortexa53.h" | ||
#endif /* defined(versal) */ | ||
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void sys_irq_restore_enable(unsigned int flags) | ||
{ | ||
Xil_ExceptionEnableMask(~flags); | ||
} | ||
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unsigned int sys_irq_save_disable(void) | ||
{ | ||
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL; | ||
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if (state != XIL_EXCEPTION_ALL) | ||
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL); | ||
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return state; | ||
} | ||
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void metal_machine_cache_flush(void *addr, unsigned int len) | ||
{ | ||
if (!addr && !len) | ||
Xil_DCacheFlush(); | ||
else | ||
Xil_DCacheFlushRange((intptr_t)addr, len); | ||
} | ||
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void metal_machine_cache_invalidate(void *addr, unsigned int len) | ||
{ | ||
if (!addr && !len) | ||
Xil_DCacheInvalidate(); | ||
else | ||
Xil_DCacheInvalidateRange((intptr_t)addr, len); | ||
} | ||
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/** | ||
* @brief poll function until some event happens | ||
*/ | ||
void metal_weak metal_generic_default_poll(void) | ||
{ | ||
metal_asm volatile("wfi"); | ||
} | ||
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void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa, | ||
size_t size, unsigned int flags) | ||
{ | ||
unsigned long section_offset; | ||
unsigned long ttb_addr; | ||
#if defined(__aarch64__) | ||
unsigned long ttb_size = (pa < 4 * GB) ? 2 * MB : 1 * GB; | ||
#else | ||
unsigned long ttb_size = 1 * MB; | ||
#endif /* defined(__aarch64__) */ | ||
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if (!flags) | ||
return va; | ||
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/* Ensure alignment on a section boundary */ | ||
pa &= ~(ttb_size - 1UL); | ||
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/* | ||
* Loop through entire region of memory (one MMU section at a time). | ||
* Each section requires a TTB entry. | ||
*/ | ||
for (section_offset = 0; section_offset < size; ) { | ||
/* Calculate translation table entry for this memory section */ | ||
ttb_addr = (pa + section_offset); | ||
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/* Write translation table entry value to entry address */ | ||
Xil_SetTlbAttributes(ttb_addr, flags); | ||
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#if defined(__aarch64__) | ||
/* | ||
* recalculate if we started below 4GB and going above in | ||
* 64bit mode | ||
*/ | ||
if (ttb_addr >= 4 * GB) | ||
ttb_size = 1 * GB; | ||
#endif | ||
section_offset += ttb_size; | ||
} | ||
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return va; | ||
} |
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/* | ||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved. | ||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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/* | ||
* @file generic/xlnx_common/zynqmp_aarch64/sys.h | ||
* @brief generic zynqmp_aarch64 system primitives for libmetal. | ||
*/ | ||
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#ifndef __METAL_GENERIC_SYS__H__ | ||
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h" | ||
#endif | ||
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#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h> | ||
#include "xscugic.h" | ||
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#ifndef __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ | ||
#define __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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#ifdef METAL_INTERNAL | ||
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#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS | ||
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static inline void sys_irq_enable(unsigned int vector) | ||
{ | ||
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector); | ||
} | ||
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static inline void sys_irq_disable(unsigned int vector) | ||
{ | ||
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector); | ||
} | ||
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#endif /* METAL_INTERNAL */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ */ |
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collect (PROJECT_LIB_HEADERS sys.h) | ||
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collect (PROJECT_LIB_SOURCES sys.c) | ||
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common) | ||
# vim: expandtab:ts=2:sw=2:smartindent |
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collect (PROJECT_LIB_HEADERS sys.h) | ||
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add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common) |
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/* | ||
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved. | ||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. | ||
* | ||
* SPDX-License-Identifier: BSD-3-Clause | ||
*/ | ||
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/* | ||
* @file generic/zynqmp_a72/sys.h | ||
* @brief generic zynqmp_a72 system primitives for libmetal. | ||
*/ | ||
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/* | ||
* The header file is still required as generic/sys.h expects | ||
* "./@PROJECT_MACHINE@/sys.h" to still exist. | ||
*/ | ||
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h> |
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