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Fixed some compilation warnings and updated kernel library
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@@ -1,23 +1,3 @@ | ||
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//Interrupt code is common for all the cortex M cores, so it has been put here | ||
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// #ifdef _ARCH_ARM7_LPC2000 | ||
// #include "interrupts_arm7.h" | ||
// #elif defined(_ARCH_CORTEXM0_STM32) || defined(_ARCH_CORTEXM3_STM32) \ | ||
// || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \ | ||
// || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \ | ||
// || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \ | ||
// || defined(_ARCH_CORTEXM4_STM32F3) || defined(_ARCH_CORTEXM4_STM32L4) \ | ||
// || defined(_ARCH_CORTEXM4_ATSAM4L) | ||
#include "interrupts_cortexMx.h" | ||
// #else | ||
// #error "Unknown arch" | ||
// #endif | ||
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// Cortex M0 and M0+ does not have some SCB registers, in order to avoid | ||
// compilation issues a flag is defined to disable code that accesses to | ||
// registers not present in these families | ||
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#if defined(_ARCH_CORTEXM0_STM32) | ||
#define _ARCH_CORTEXM0 | ||
#endif |
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