aarch64

OpenSmalltalk · Jan 21, 2019 · 16b4df1 · 16b4df1
1 parent bbfe0ff
commit 16b4df1
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Showing 5 changed files with 32 additions and 4 deletions.
diff --git a/platforms/Cross/plugins/IA32ABI/arm32abicc.c b/platforms/Cross/plugins/IA32ABI/arm32abicc.c
@@ -91,7 +91,7 @@ sqInt callIA32IntegralReturn(SIGNATURE) {
             double d0, double d1, double d2, double d3,
             double d4, double d5, double d6, double d7);
   long r;
-#include "dabusinessARM.h"
+#include "dabusinessARM32.h"
 }
 
 /*
@@ -103,7 +103,7 @@ sqInt callIA32FloatReturn(SIGNATURE) {
              double d0, double d1, double d2, double d3,
              double d4, double d5, double d6, double d7);
   float r;
-#include "dabusinessARM.h"
+#include "dabusinessARM32.h"
 }
 
 /*

diff --git a/platforms/Cross/plugins/IA32ABI/ia32abi.h b/platforms/Cross/plugins/IA32ABI/ia32abi.h
@@ -49,6 +49,11 @@ extern sqInt callIA32DoubleReturn  (SIGNATURE);
 #elif defined(__powerpc__) || defined(PPC) || defined(_POWER) || defined(_IBMR2) || defined(__ppc__)
 # define INT_REG_ARGS long,long,long,long,long,long,long,long,
 # define DBL_REG_ARGS /* none */
+#elif defined(__ARM_ARCH_ISA_A64) || defined(__arm64__) || defined(__aarch64__) || defined(ARM64)
+# undef thunkEntryType
+# define thunkEntryType long long
+# define INT_REG_ARGS long,long,long,long,long,long,long,long,
+# define DBL_REG_ARGS double,double,double,double,double,double,double,double,
 #elif defined(__ARM_ARCH__) || defined(__arm__) || defined(__arm32__) || defined(ARM32)
 # undef thunkEntryType
 # define thunkEntryType long long

diff --git a/platforms/Cross/plugins/IA32ABI/xabicc.c b/platforms/Cross/plugins/IA32ABI/xabicc.c
@@ -15,6 +15,8 @@
 # else
 #	include "x64sysvabicc.c"
 # endif
+#elif defined(__ARM_ARCH_ISA_A64) || defined(__aarch64__) || defined(__arm64__) || defined(ARM64)
+# include "arm64abicc.c"
 #elif defined(__ARM_ARCH__) || defined(__arm__) || defined(__arm32__) || defined(ARM32) || defined(_M_ARM)
 # include "arm32abicc.c"
 #else

diff --git a/platforms/Cross/vm/sqAtomicOps.h b/platforms/Cross/vm/sqAtomicOps.h
@@ -46,7 +46,7 @@
 #  else /* unknown platform */
 #  endif
 
-#elif defined(x86_64) || defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(__amd64__) || defined(x64) || defined(_M_AMD64) || defined(_M_X64) || defined(_M_IA64)
+#elif defined(x86_64) || defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(__amd64__) || defined(x64) || defined(_M_AMD64) || defined(_M_X64) || defined(_M_IA64) || defined(ARM64) || defined(__ARCH_ARM_ISA_A64)
 
 #  define IS_64_BIT_ARCH 1
 

diff --git a/platforms/Cross/vm/sqCogStackAlignment.h b/platforms/Cross/vm/sqCogStackAlignment.h
@@ -22,7 +22,13 @@
 # endif
 #endif
 
-#if defined(__arm__) || defined(__arm32__) || defined(ARM32)
+#if defined(__arm64__) || defined(__aarch64__) || defined(ARM64)
+/* Quad-byte stack alignment on ARM64 is required.
+   (SP mod 16) == 0
+ */
+# define STACK_ALIGN_BYTES 16
+# define STACK_FP_ALIGNMENT 8
+#elif defined(__arm__) || defined(__arm32__) || defined(ARM32)
 /* 8-byte stack alignment on ARM32 is required for instructions which
  * require 8-byte aligned addresses to access doubles in memory.
  */
@@ -70,6 +76,21 @@
 #   define getsp() ({ register usqIntptr_t sp;					\
 					  asm volatile ("movl %%esp,%0" : "=r"(sp) : );	\
 					  sp; })
+#  endif
+# elif defined(__arm64__) || defined(__aarch64__) || defined(ARM64)
+	/* https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Extended-Asm
+	 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/index.html
+	 */
+#  if __GNUC__
+#   define getfp() ({ usqIntptr_t fp;								\
+					  asm volatile ("mov x0, x29" : "=r"(x29) : );	\
+					  fp; })
+#   define getsp() ({ usqIntptr_t sp;								\
+					  asm volatile ("mov x0, sp" : "=r"(sp) : );	\
+					  sp; })
+
+# define setsp(sp) asm volatile ("ldr x16, %0 \n\t" "mov sp, x16"  : : "m"(sp) )
+
 #  endif
 # elif defined(__arm__) || defined(__arm32__) || defined(ARM32)
 	/* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0041c/Cegbidie.html