Prepare to merge master (#2814)

.github/workflows/emu.yml

@@ -11,6 +11,7 @@ jobs:
   generate-verilog:
     runs-on: bosc
     continue-on-error: false
+    timeout-minutes: 900
     name: Generate Verilog
     steps:
       - uses: actions/checkout@v2
@@ -31,26 +32,23 @@ jobs:
           bash .github/workflows/check-usage.sh "BoringUtils" $GITHUB_WORKSPACE
       - name: generate verilog file
         run:
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2 --mfc
       - name: check verilog
         run:
           python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl/XSTop.v
       - name: build MinimalConfig Release emu
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
-            --threads 4 --config MinimalConfig --release
+            --threads 8 --config MinimalConfig --release --mfc
       - name: run MinimalConfig - Linux
         run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 4 --numa --ci linux-hello-opensbi 2> perf.log
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci linux-hello-opensbi 2> perf.log
           cat perf.log | sort
   emu-basics:
     runs-on: bosc
     continue-on-error: false
     timeout-minutes: 900
     name: EMU - Basics
-    strategy:
-      matrix:
-        mfc-arg: ["", "--mfc"]
     steps:
       - uses: actions/checkout@v2
         with:
@@ -70,7 +68,7 @@ jobs:
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
       - name: Build EMU
         run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 8 ${{ matrix.mfc-arg }}
+          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 8 --mfc
       - name: Basic Test - cputest
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --ci cputest 2> /dev/zero
@@ -129,7 +127,7 @@ jobs:
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
             --dramsim3 /nfs/home/share/ci-workloads/DRAMsim3            \
-            --with-dramsim3 --threads 16
+            --with-dramsim3 --threads 16 --mfc
       - name: SPEC06 Test - mcf
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --max-instr 5000000 --numa --ci mcf 2> perf.log

.github/workflows/nightly.yml

@@ -8,8 +8,8 @@ jobs:
   build:
     runs-on: bosc
     continue-on-error: false
-    # At most 12 hours to finish (before 11:33 UTC+8).
-    timeout-minutes: 720
+    # At most 10 hours to finish (before 9:33 UTC+8).
+    timeout-minutes: 600
     # Build + 8 checkpoints * 1-hour timeout
     name: Nightly Regression - Checkpoints
     steps:
@@ -19,7 +19,6 @@ jobs:
       - name: set env
         run: |
           export HEAD_SHA=${{ github.run_number }}
-          echo "NOOP_HOME=$GITHUB_WORKSPACE" >> $GITHUB_ENV
           echo "NEMU_HOME=/nfs/home/share/ci-workloads/NEMU" >> $GITHUB_ENV
           echo "PERF_HOME=/nfs/home/ci-runner/xs-perf/${HEAD_SHA}" >> $GITHUB_ENV
           echo "WAVE_HOME=/nfs/home/ci-runner/xs-wave/${HEAD_SHA}" >> $GITHUB_ENV

.gitmodules

@@ -16,6 +16,9 @@
 [submodule "utility"]
 	path = utility
 	url = https://github.com/OpenXiangShan/utility
+[submodule "yunsuan"]
+	path = yunsuan
+	url = https://github.com/OpenXiangShan/YunSuan.git
 [submodule "coupledL2"]
 	path = coupledL2
 	url = https://github.com/OpenXiangShan/coupledL2

Makefile

@@ -38,13 +38,20 @@ CONFIG ?= DefaultConfig
 NUM_CORES ?= 1
 MFC ?= 0
 
+
+ifeq ($(MAKECMDGOALS),)
+GOALS = verilog
+else
+GOALS = $(MAKECMDGOALS)
+endif
+
 # common chisel args
 ifeq ($(MFC),1)
 CHISEL_VERSION = chisel
 FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
 SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
 MFC_ARGS = --dump-fir \
-           --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
+           --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
 RELEASE_ARGS += $(MFC_ARGS)
 DEBUG_ARGS += $(MFC_ARGS)
 PLDM_ARGS += $(MFC_ARGS)
@@ -86,9 +93,12 @@ override SIM_ARGS += --with-constantin
 endif
 
 # emu for the release version
-RELEASE_ARGS += --disable-all --remove-assert --fpga-platform
+RELEASE_ARGS += --fpga-platform --disable-all --remove-assert
 DEBUG_ARGS   += --enable-difftest
 PLDM_ARGS    += --fpga-platform --enable-difftest
+ifeq ($(GOALS),verilog)
+RELEASE_ARGS += --disable-always-basic-diff
+endif
 ifeq ($(RELEASE),1)
 override SIM_ARGS += $(RELEASE_ARGS)
 else ifeq ($(PLDM),1)
@@ -138,7 +148,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	@date -R | tee -a $(TIMELOG)
 	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP)    \
 		-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)                          \
-		--num-cores $(NUM_CORES) $(SIM_ARGS)
+		--num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
 ifeq ($(MFC),1)
 	$(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
 	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"

build.sc

@@ -118,6 +118,13 @@ trait Utility extends HasChisel {
 
 }
 
+object yunsuan extends Cross[YunSuan]("chisel", "chisel3")
+trait YunSuan extends HasChisel {
+
+  override def millSourcePath = os.pwd / "yunsuan"
+
+}
+
 object huancun extends Cross[HuanCun]("chisel", "chisel3")
 trait HuanCun extends millbuild.huancun.common.HuanCunModule with HasChisel {
 
@@ -171,15 +178,22 @@ trait XiangShanModule extends ScalaModule {
 
   def utilityModule: ScalaModule
 
+  def yunsuanModule: ScalaModule
+
   override def moduleDeps = super.moduleDeps ++ Seq(
     rocketModule,
     difftestModule,
     huancunModule,
     coupledL2Module,
+    yunsuanModule,
     fudianModule,
     utilityModule,
   )
 
+  val resourcesPATH = os.pwd.toString() + "/src/main/resources"
+  val envPATH = sys.env("PATH") + ":" + resourcesPATH
+
+  override def forkEnv = Map("PATH" -> envPATH)
 }
 
 object xiangshan extends Cross[XiangShan]("chisel", "chisel3")
@@ -199,14 +213,20 @@ trait XiangShan extends XiangShanModule with HasChisel {
 
   def utilityModule = utility(crossValue)
 
-  override def forkArgs = Seq("-Xmx20G", "-Xss256m")
+  def yunsuanModule = yunsuan(crossValue)
+
+  override def forkArgs = Seq("-Xmx40G", "-Xss256m")
 
   override def sources = T.sources {
     super.sources() ++ Seq(PathRef(millSourcePath / "src" / crossValue / "main" / "scala"))
   }
 
+  override def ivyDeps = super.ivyDeps() ++ Agg(
+    defaultVersions(crossValue)("chiseltest"),
+  )
+
   object test extends SbtModuleTests with TestModule.ScalaTest {
-    override def forkArgs = Seq("-Xmx20G", "-Xss256m")
+    override def forkArgs = Seq("-Xmx40G", "-Xss256m")
 
     override def sources = T.sources {
       super.sources() ++ Seq(PathRef(millSourcePath / "src" / crossValue / "test" / "scala"))
@@ -215,5 +235,10 @@ trait XiangShan extends XiangShanModule with HasChisel {
     override def ivyDeps = super.ivyDeps() ++ Agg(
       defaultVersions(crossValue)("chiseltest")
     )
+
+    val resourcesPATH = os.pwd.toString() + "/src/main/resources"
+    val envPATH = sys.env("PATH") + ":" + resourcesPATH
+
+    override def forkEnv = Map("PATH" -> envPATH)
   }
 }

src/main/scala/device/RocketDebugWrapper.scala

@@ -59,7 +59,9 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
     val io = IO(new DebugModuleIO)
     debug.module.io.tl_reset := io.reset // this should be TL reset
     debug.module.io.tl_clock := io.clock.asClock // this should be TL clock
-    debug.module.io.hartIsInReset := io.resetCtrl.hartIsInReset
+    withClock(io.clock.asClock) {
+      debug.module.io.hartIsInReset := RegNext(io.resetCtrl.hartIsInReset)
+    }
     io.resetCtrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
 
     io.debugIO.clockeddmi.foreach { dbg => debug.module.io.dmi.get <> dbg } // not connected in current case since we use dtm
@@ -104,7 +106,9 @@ object XSDebugModuleParams {
       maxSupportedSBAccess = xlen,
       hasBusMaster = true,
       baseAddress = BigInt(0x38020000),
-      nScratch = 2
+      nScratch = 2,
+      crossingHasSafeReset = false,
+      hasHartResets = true,
     )
   }
 }
@@ -122,6 +126,9 @@ class SimJTAG(tickDelay: Int = 50)(implicit val p: Parameters) extends ExtModule
   val exit = IO(Output(UInt(32.W)))
 
   def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Reset, done: Bool, tbsuccess: Bool) = {
+    if (!dutio.TRSTn.isEmpty) {
+      dutio.TRSTn.get := jtag.TRSTn.getOrElse(false.B) || !tbreset.asBool
+    }
     dutio.TCK := jtag.TCK
     dutio.TMS := jtag.TMS
     dutio.TDI := jtag.TDI

src/main/scala/top/ArgParser.scala

@@ -93,6 +93,10 @@ object ArgParser {
           nextOption(config.alter((site, here, up) => {
             case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDifftest = true)
           }), tail)
+        case "--disable-always-basic-diff" :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case DebugOptionsKey => up(DebugOptionsKey).copy(AlwaysBasicDiff = false)
+          }), tail)
         case "--enable-log" :: tail =>
           nextOption(config.alter((site, here, up) => {
             case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDebug = true)

src/main/scala/top/BusPerfMonitor.scala

@@ -84,6 +84,7 @@ class BusPerfMonitorImp(outer: BusPerfMonitor, name: String, stat_latency: Boole
           XSPerfAccumulate(s"${clientName}_${channelName}_${op}_stall",
             i.U === d.opcode && chn.valid && !chn.ready
           )
+        case e: TLBundleE => throw new IllegalArgumentException("Cannot reach here")
       }
     }
   }

src/main/scala/top/Configs.scala

@@ -26,14 +26,20 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
 import xiangshan.frontend.icache.ICacheParameters
 import freechips.rocketchip.devices.debug._
-import freechips.rocketchip.tile.MaxHartIdBits
+import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
+import system._
+import utility._
+import utils._
+import huancun._
+import xiangshan._
 import xiangshan.backend.dispatch.DispatchParameters
-import xiangshan.backend.exu.ExuParameters
+import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
 import xiangshan.cache.DCacheParameters
 import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
 import device.{EnableJtag, XSDebugModuleParams}
 import huancun._
 import coupledL2._
+import xiangshan.frontend.icache.ICacheParameters
 
 class BaseConfig(n: Int) extends Config((site, here, up) => {
   case XLen => 64
@@ -57,48 +63,46 @@ class MinimalConfig(n: Int = 1) extends Config(
   new BaseConfig(n).alter((site, here, up) => {
     case XSTileKey => up(XSTileKey).map(
       p => p.copy(
-        DecodeWidth = 2,
-        RenameWidth = 2,
-        CommitWidth = 2,
+        DecodeWidth = 6,
+        RenameWidth = 6,
+        CommitWidth = 6,
         FetchWidth = 4,
-        IssQueSize = 8,
-        NRPhyRegs = 64,
-        VirtualLoadQueueSize = 16,
+        VirtualLoadQueueSize = 24,
         LoadQueueRARSize = 16,
         LoadQueueRAWSize = 12,
-        LoadQueueReplaySize = 12,
+        LoadQueueReplaySize = 24,
         LoadUncacheBufferSize = 8,
         LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
         RollbackGroupSize = 8,
-        StoreQueueSize = 12,
+        StoreQueueSize = 20,
         StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
         StoreQueueForwardWithMask = true,
-        RobSize = 32,
+        RobSize = 48,
+        RabSize = 96,
         FtqSize = 8,
-        IBufSize = 16,
-        IBufNBank = 2,
+        IBufSize = 24,
+        IBufNBank = 6,
         StoreBufferSize = 4,
         StoreBufferThreshold = 3,
-        LoadPipelineWidth = 2,
-        StorePipelineWidth = 2,
+        IssueQueueSize = 8,
+        IssueQueueCompEntrySize = 4,
         dpParams = DispatchParameters(
           IntDqSize = 12,
           FpDqSize = 12,
           LsDqSize = 12,
-          IntDqDeqWidth = 4,
+          IntDqDeqWidth = 8,
           FpDqDeqWidth = 4,
-          LsDqDeqWidth = 4
+          LsDqDeqWidth = 6
         ),
-        exuParameters = ExuParameters(
-          JmpCnt = 1,
-          AluCnt = 2,
-          MulCnt = 0,
-          MduCnt = 1,
-          FmacCnt = 1,
-          FmiscCnt = 1,
-          FmiscDivSqrtCnt = 0,
-          LduCnt = 2,
-          StuCnt = 2
+        intPreg = IntPregParams(
+          numEntries = 64,
+          numRead = None,
+          numWrite = None,
+        ),
+        vfPreg = VfPregParams(
+          numEntries = 160,
+          numRead = Some(14),
+          numWrite = None,
         ),
         icacheParameters = ICacheParameters(
           nSets = 64, // 16KB ICache
@@ -145,6 +149,13 @@ class MinimalConfig(n: Int = 1) extends Config(
           outsideRecvFlush = true,
           outReplace = false
         ),
+        hytlbParameters = TLBParameters(
+          name = "hytlb",
+          NWays = 4,
+          partialStaticPMP = true,
+          outsideRecvFlush = true,
+          outReplace = false
+        ),
         pftlbParameters = TLBParameters(
           name = "pftlb",
           NWays = 4,