FuConfig: split dataBits into destDataBits and srcDataBits for distin…

…guish input and output data width

src/main/scala/xiangshan/backend/Bundles.scala

@@ -542,7 +542,7 @@ object Bundles {
   class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle {
     val fuType        = FuType()
     val fuOpType      = FuOpType()
-    val src           = Vec(params.numRegSrc, UInt(params.dataBitsMax.W))
+    val src           = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W))
     val imm           = UInt(32.W)
     val robIdx        = new RobPtr
     val iqIdx         = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet
@@ -651,7 +651,7 @@ object Bundles {
   )(implicit
     val p: Parameters
   ) extends Bundle with BundleSource with HasXSParameter {
-    val data         = UInt(params.dataBitsMax.W)
+    val data         = UInt(params.destDataBitsMax.W)
     val pdest        = UInt(params.wbPregIdxWidth.W)
     val robIdx       = new RobPtr
     val intWen       = if (params.needIntWen)   Some(Bool())                  else None
@@ -799,7 +799,7 @@ object Bundles {
   )(implicit
     val p: Parameters
   ) extends Bundle {
-    val data  = UInt(params.dataBitsMax.W)
+    val data  = UInt(params.destDataBitsMax.W)
     val pdest = UInt(params.wbPregIdxWidth.W)
   }
 

src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala

@@ -124,7 +124,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
       val imm = ImmExtractor(
         immInfo(exuIdx).imm,
         immInfo(exuIdx).immType,
-        exuInput.bits.params.dataBitsMax,
+        exuInput.bits.params.destDataBitsMax,
         exuInput.bits.params.immType.map(_.litValue)
       )
       val immLoadSrc0 = SignExt(ImmUnion.U.toImm32(immInfo(exuIdx).imm(immInfo(exuIdx).imm.getWidth - 1, ImmUnion.I.len)), XLEN)

src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala

@@ -40,7 +40,8 @@ case class ExeUnitParams(
   val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max
   val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max
   val numSrc: Int = fuConfigs.map(_.numSrc).max
-  val dataBitsMax: Int = fuConfigs.map(_.dataBits).max
+  val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max
+  val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max
   val readIntRf: Boolean = numIntSrc > 0
   val readFpRf: Boolean = numFpSrc > 0
   val readVecRf: Boolean = numVecSrc > 0

src/main/scala/xiangshan/backend/fu/FuConfig.scala

@@ -26,7 +26,8 @@ import xiangshan.backend.datapath.DataConfig._
   * @param writeVlRf the $fu write vl regfiles
   * @param writeFflags the $fu write fflags csr
   * @param writeVxsat the $fu write vxsat csr
-  * @param dataBits the width of data in the $fu
+  * @param destDataBits the width of output data in the $fu
+  * @param srcDataBits the width of input data in the $fu, the default value is destDataBits
   * @param latency the latency of instuction executed in the $fu
   * @param hasInputBuffer if the $fu has input buffer
   * @param exceptionOut the $fu can produce these exception
@@ -57,7 +58,8 @@ case class FuConfig (
   writeFakeIntRf: Boolean = false,
   writeFflags   : Boolean = false,
   writeVxsat    : Boolean = false,
-  dataBits      : Int = 64,
+  destDataBits  : Int = 64,
+  srcDataBits   : Option[Int] = None,
   latency       : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option))
   hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false),
   exceptionOut  : Seq[Int] = Seq(),
@@ -260,7 +262,8 @@ object FuConfig {
     writeVecRf = true,
     writeV0Rf = true,
     latency = CertainLatency(0),
-    dataBits = 128,
+    destDataBits = 128,
+    srcDataBits = Some(64),
     immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS),
   )
 
@@ -276,7 +279,8 @@ object FuConfig {
     writeVecRf = true,
     writeV0Rf = true,
     latency = CertainLatency(0),
-    dataBits = 128,
+    destDataBits = 128,
+    srcDataBits = Some(64),
   )
 
   val CsrCfg: FuConfig = FuConfig (
@@ -523,7 +527,7 @@ object FuConfig {
     latency = CertainLatency(1),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI),
   )
@@ -543,7 +547,7 @@ object FuConfig {
     latency = CertainLatency(2),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
   )
 
@@ -560,7 +564,7 @@ object FuConfig {
     latency = UncertainLatency(),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
   )
 
@@ -577,7 +581,7 @@ object FuConfig {
     latency = CertainLatency(2),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS),
   )
@@ -596,7 +600,7 @@ object FuConfig {
     latency = CertainLatency(2),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
   )
 
@@ -615,7 +619,7 @@ object FuConfig {
     latency = CertainLatency(1),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     needSrcFrm = true,
   )
@@ -634,7 +638,7 @@ object FuConfig {
     latency = CertainLatency(3),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     needSrcFrm = true,
   )
@@ -653,7 +657,7 @@ object FuConfig {
     latency = UncertainLatency(),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     needSrcFrm = true,
   )
@@ -672,7 +676,7 @@ object FuConfig {
     latency = CertainLatency(2),
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
     exceptionOut = Seq(illegalInstr),
     needSrcFrm = true,
   )
@@ -689,7 +693,7 @@ object FuConfig {
     writeIntRf = true,
     writeFflags = true,
     latency = CertainLatency(1),
-    dataBits = 64,
+    destDataBits = 64,
     needSrcFrm = true,
   )
 
@@ -704,7 +708,7 @@ object FuConfig {
     writeFpRf = true,
     writeFflags = true,
     latency = CertainLatency(3),
-    dataBits = 64,
+    destDataBits = 64,
     needSrcFrm = true,
   )
 
@@ -719,7 +723,7 @@ object FuConfig {
     writeFpRf = true,
     writeFflags = true,
     latency = UncertainLatency(),
-    dataBits = 64,
+    destDataBits = 64,
     needSrcFrm = true,
   )
 
@@ -735,7 +739,7 @@ object FuConfig {
     writeIntRf = true,
     writeFflags = true,
     latency = CertainLatency(2),
-    dataBits = 64,
+    destDataBits = 64,
     needSrcFrm = true,
   )
 
@@ -756,7 +760,7 @@ object FuConfig {
     hasLoadError = true,
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
   )
 
   val VstuCfg: FuConfig = FuConfig (
@@ -774,7 +778,7 @@ object FuConfig {
     hasLoadError = true,
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
   )
 
   val VseglduSeg: FuConfig = FuConfig (
@@ -794,7 +798,7 @@ object FuConfig {
     hasLoadError = true,
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
   )
 
   val VsegstuCfg: FuConfig = FuConfig(
@@ -812,7 +816,7 @@ object FuConfig {
     hasLoadError = true,
     vconfigWakeUp = true,
     maskWakeUp = true,
-    dataBits = 128,
+    destDataBits = 128,
   )
 
   def allConfigs = Seq(

src/main/scala/xiangshan/backend/fu/FuncUnit.scala

@@ -53,15 +53,15 @@ class FuncUnitCtrlOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle
 
 class FuncUnitDataInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
   val src       = MixedVec(cfg.genSrcDataVec)
-  val imm       = UInt(cfg.dataBits.W)
+  val imm       = UInt(cfg.destDataBits.W)
   val pc        = OptionWrapper(cfg.needPc, UInt(VAddrData().dataWidth.W))
 
   def getSrcVConfig : UInt = src(cfg.vconfigIdx)
   def getSrcMask    : UInt = src(cfg.maskSrcIdx)
 }
 
 class FuncUnitDataOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
-  val data      = UInt(cfg.dataBits.W)
+  val data      = UInt(cfg.destDataBits.W)
   val fflags    = OptionWrapper(cfg.writeFflags, UInt(5.W))
   val vxsat     = OptionWrapper(cfg.writeVxsat, Vxsat())
   val pc        = OptionWrapper(cfg.isFence, UInt(VAddrData().dataWidth.W))

src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala

@@ -44,7 +44,7 @@ class IntFPToVec(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cf
   private val scalaData = Mux(isImm, in.data.src(1), in.data.src(0))
   // vsew is the lowest 2 bits of fuOpType
   private val vsew = in.ctrl.fuOpType(1, 0)
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
 
   private val outNAN = Seq(
     Cat(0.U, Fill(3, 1.U), 1.U, 0.U(3.W)),

src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala

@@ -10,7 +10,7 @@ import xiangshan.backend.fu.FuConfig
 
 class DivUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
 
-  val xlen = cfg.dataBits
+  val xlen = cfg.destDataBits
 
   val func = io.in.bits.ctrl.fuOpType
   val ctrl = Wire(new MulDivCtrl)
@@ -30,7 +30,7 @@ class DivUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
   val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire)
   val ctrlReg = RegEnable(ctrl, io.in.fire)
 
-  val divDataModule = Module(new SRT16DividerDataModule(cfg.dataBits))
+  val divDataModule = Module(new SRT16DividerDataModule(cfg.destDataBits))
 
   val kill_w = io.in.bits.ctrl.robIdx.needFlush(io.flush)
   val kill_r = !divDataModule.io.in_ready && robIdxReg.needFlush(io.flush)

src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala

@@ -15,7 +15,7 @@ class JumpUnit(cfg: FuConfig)(implicit p: Parameters) extends PipedFuncUnit(cfg)
 
   // associated with AddrData's position of JmpCfg.srcData
   private val src = io.in.bits.data.src(0)
-  private val pc = SignExt(io.in.bits.data.pc.get, cfg.dataBits)
+  private val pc = SignExt(io.in.bits.data.pc.get, cfg.destDataBits)
   private val immMin = io.in.bits.data.imm
   private val func = io.in.bits.ctrl.fuOpType
   private val isRVC = io.in.bits.ctrl.preDecode.get.isRVC

src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala

@@ -12,7 +12,7 @@ class MulUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
 {
   override def latency: Int = 2
 
-  private val xlen = cfg.dataBits
+  private val xlen = cfg.destDataBits
 
   val func = io.in.bits.ctrl.fuOpType
   val src = io.in.bits.data.src
@@ -35,7 +35,7 @@ class MulUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
   )
 
   // len should be xlen + 1
-  private val len = cfg.dataBits + 1
+  private val len = cfg.destDataBits + 1
   private val mulDataModule = Module(new ArrayMulDataModule(len))
 
   mulDataModule.io.a := LookupTree(

src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala

@@ -17,7 +17,7 @@ class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala

@@ -17,7 +17,7 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala

@@ -17,7 +17,7 @@ class VFDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUn
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfdiv OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala

@@ -17,7 +17,7 @@ class VFMA(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala

@@ -136,7 +136,7 @@ class VIAluFix(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(c
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VialuFixType.dummy, "VialuF OpType not supported")
 
   // config params
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala

@@ -16,7 +16,7 @@ class VIDiv(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(c
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VidivType.dummy, "Vfdiv OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
 
   // modules
   private val vidiv = Module(new VectorIdiv)

src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala

@@ -46,7 +46,7 @@ class VIMacU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VimacType.dummy, "VialuF OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
 

src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala

@@ -91,7 +91,7 @@ class VIPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VipuType.dummy, "VIPU OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
   private val needClearVs1 = (VipuType.vcpop_m === io.in.bits.ctrl.fuOpType && vuopIdx === 0.U) ||

src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala

@@ -32,7 +32,7 @@ class VPPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VpermType.dummy, "VpermType OpType not supported")
 
   // params alias
-  private val dataWidth = cfg.dataBits
+  private val dataWidth = cfg.destDataBits
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
   private val vppuNeedClearMask = (VpermType.vcompress === io.in.bits.ctrl.fuOpType) && (vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U)