chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`

.github/workflows/emu.yml

@@ -34,7 +34,7 @@ jobs:
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2
       - name: check verilog
         run:
-          python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/XSTop.v
+          python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/rtl/XSTop.v
       - name: build MinimalConfig Release emu
         run: |
           python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \

Makefile

@@ -15,15 +15,16 @@
 #***************************************************************************************
 
 BUILD_DIR = ./build
+RTL_DIR = $(BUILD_DIR)/rtl
 
 TOP = XSTop
 SIM_TOP = SimTop
 
 FPGATOP = top.TopMain
 SIMTOP  = top.SimTop
 
-TOP_V = $(BUILD_DIR)/$(TOP).v
-SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
+TOP_V = $(RTL_DIR)/$(TOP).v
+SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v
 
 SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
 TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
@@ -37,28 +38,12 @@ CONFIG ?= DefaultConfig
 NUM_CORES ?= 1
 MFC ?= 0
 
-# firtool check and download
-FIRTOOL_VERSION = 1.61.0
-FIRTOOL_URL = https://github.com/llvm/circt/releases/download/firtool-$(FIRTOOL_VERSION)/firrtl-bin-linux-x64.tar.gz
-FIRTOOL_PATH = $(shell which firtool 2>/dev/null)
-CACHE_FIRTOOL_PATH = $(HOME)/.cache/xiangshan/firtool-$(FIRTOOL_VERSION)/bin/firtool
-ifeq ($(MFC),1)
-ifeq ($(FIRTOOL_PATH),)
-ifeq ($(wildcard $(CACHE_FIRTOOL_PATH)),)
-$(info [INFO] Firtool not found in your PATH.)
-$(info [INFO] Downloading from $(FIRTOOL_URL))
-$(shell mkdir -p $(HOME)/.cache/xiangshan && curl -L $(FIRTOOL_URL) | tar -xzC $(HOME)/.cache/xiangshan)
-endif
-FIRTOOL_ARGS = --firtool-binary-path $(CACHE_FIRTOOL_PATH)
-endif
-endif
-
 # common chisel args
 ifeq ($(MFC),1)
 CHISEL_VERSION = chisel
 FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
 SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
-MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \
+MFC_ARGS = --dump-fir \
            --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
 RELEASE_ARGS += $(MFC_ARGS)
 DEBUG_ARGS += $(MFC_ARGS)
@@ -122,8 +107,8 @@ $(TOP_V): $(SCALA_FILE)
 		-td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS)                    \
 		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
 ifeq ($(MFC),1)
-	$(SPLIT_VERILOG) $(BUILD_DIR) $(TOP).v
-	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
+	$(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
+	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
 endif
 	$(SED_CMD) $@
 	@git log -n 1 >> .__head__
@@ -144,8 +129,8 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 		-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)                          \
 		--num-cores $(NUM_CORES) $(SIM_ARGS)
 ifeq ($(MFC),1)
-	$(SPLIT_VERILOG) $(BUILD_DIR) $(SIM_TOP).v
-	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)"
+	$(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
+	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
 endif
 	$(SED_CMD) $@
 	@git log -n 1 >> .__head__

build.sc

@@ -26,8 +26,8 @@ val defaultScalaVersion = "2.13.10"
 
 def defaultVersions(chiselVersion: String) = chiselVersion match {
   case "chisel" => Map(
-    "chisel"        -> ivy"org.chipsalliance::chisel:6.0.0-RC1",
-    "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.0.0-RC1",
+    "chisel"        -> ivy"org.chipsalliance::chisel:6.0.0",
+    "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.0.0",
     "chiseltest"    -> ivy"edu.berkeley.cs::chiseltest:5.0.2"
   )
   case "chisel3" => Map(

scripts/xiangshan.py

@@ -417,7 +417,7 @@ def run_ci(self, test):
                     print("copy wave file to " + self.args.wave_home)
                     self.__exec_cmd(f"cp $NOOP_HOME/build/*.vcd $WAVE_HOME")
                     self.__exec_cmd(f"cp $NOOP_HOME/build/emu $WAVE_HOME")
-                    self.__exec_cmd(f"cp $NOOP_HOME/build/SimTop.v $WAVE_HOME")
+                    self.__exec_cmd(f"cp $NOOP_HOME/build/rtl/SimTop.v $WAVE_HOME")
                     self.__exec_cmd(f"cp $NOOP_HOME/build/*.db $WAVE_HOME")
                 return ret
         return 0
@@ -440,7 +440,7 @@ def run_ci_vcs(self, test):
                     print("copy wave file to " + self.args.wave_home)
                     self.__exec_cmd(f"cp $NOOP_HOME/build/*.vcd $WAVE_HOME")
                     self.__exec_cmd(f"cp $NOOP_HOME/build/emu $WAVE_HOME")
-                    self.__exec_cmd(f"cp $NOOP_HOME/build/SimTop.v $WAVE_HOME")
+                    self.__exec_cmd(f"cp $NOOP_HOME/build/rtl/SimTop.v $WAVE_HOME")
                     self.__exec_cmd(f"cp $NOOP_HOME/build/*.db $WAVE_HOME")
                 return ret
         return 0

src/main/scala/utils/Trigger.scala

@@ -27,7 +27,7 @@ object TriggerCmp {
     val equal = actual === tdata
     val greater = actual >= tdata
     val less = actual <= tdata
-    val res = MuxLookup(matchType, false.B,
+    val res = MuxLookup(matchType, false.B)(
       Array(0.U -> equal,
           2.U -> greater,
           3.U -> less))
@@ -78,7 +78,7 @@ object TriggerCmpConsecutive {
 
     val ret = Wire(Vec(len1, Bool()))
 
-    ret.zipWithIndex.map{case (r, i) => r := MuxLookup(matchType, false.B,
+    ret.zipWithIndex.map{case (r, i) => r := MuxLookup(matchType, false.B)(
       Array(0.U -> overallEqual(i),
         2.U -> overallGreater(i),
         3.U -> overallLess(i))) && enable}

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -268,7 +268,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     6.U -> I_Trigger, 7.U -> S_Trigger,
     8.U -> I_Trigger, 9.U -> L_Trigger
   )
-  def TypeLookup(select: UInt) = MuxLookup(select, I_Trigger, type_config)
+  def TypeLookup(select: UInt) = MuxLookup(select, I_Trigger)(type_config)
 
   val tdata1Phy = RegInit(VecInit(List.fill(10) {(2L << 60L).U(64.W)})) // init ttype 2
   val tdata2Phy = Reg(Vec(10, UInt(64.W)))
@@ -327,13 +327,13 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     res
   }
 
-  csrio.customCtrl.frontend_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U, Seq(
+  csrio.customCtrl.frontend_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U)(Seq(
     0.U -> 0.U,
     1.U -> 1.U,
     6.U -> 2.U,
     8.U -> 3.U
   ))
-  csrio.customCtrl.mem_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U, Seq(
+  csrio.customCtrl.mem_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U)(Seq(
     2.U -> 0.U,
     3.U -> 1.U,
     4.U -> 2.U,

src/main/scala/xiangshan/backend/fu/Multiplier.scala

@@ -79,7 +79,7 @@ class ArrayMulDataModule(len: Int) extends Module {
   var last_x = WireInit(0.U(3.W))
   for(i <- Range(0, len, 2)){
     val x = if(i==0) Cat(a(1,0), 0.U(1.W)) else if(i+1==len) SignExt(a(i, i-1), 3) else a(i+1, i-1)
-    val pp_temp = MuxLookup(x, 0.U, Seq(
+    val pp_temp = MuxLookup(x, 0.U)(Seq(
       1.U -> b_sext,
       2.U -> b_sext,
       3.U -> bx2,
@@ -88,7 +88,7 @@ class ArrayMulDataModule(len: Int) extends Module {
       6.U -> neg_b
     ))
     val s = pp_temp(len)
-    val t = MuxLookup(last_x, 0.U(2.W), Seq(
+    val t = MuxLookup(last_x, 0.U(2.W))(Seq(
       4.U -> 2.U(2.W),
       5.U -> 1.U(2.W),
       6.U -> 1.U(2.W)

src/main/scala/xiangshan/backend/fu/SRT16Divider.scala

@@ -174,7 +174,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
   val rCarryInit = 0.U(itn_len.W)
 
   val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___
-  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W),
+  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W))(
     Array(
       0.U -> "b00100".U(5.W),
       1.U -> "b00100".U(5.W),
@@ -186,7 +186,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
       7.U -> "b01000".U(5.W),
     )
   )
-  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W),
+  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W))(
     Array(
       0.U -> "b01100".U(5.W),
       1.U -> "b01110".U(5.W),
@@ -240,10 +240,10 @@ class SRT16DividerDataModule(len: Int) extends Module {
 
   // Give values to the regs and wires above...
   val dForLookup = dPos(len-2, len-4)
-  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
-                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
-                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
-                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
+  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
+                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
+                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
+                  Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
   )
   udNeg := VecInit( Cat(SignExt(dPos, 66), 0.U(2.W)),
                     Cat(SignExt(dPos, 67), 0.U(1.W)),

src/main/scala/xiangshan/backend/fu/SRT4Divider.scala

@@ -181,7 +181,7 @@ class SRT4DividerDataModule(len: Int) extends Module {
 
   // obtaining 1st quotient
   val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___
-  val mInitPos1 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b00100".U(5.W),
+  val mInitPos1 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b00100".U(5.W))(
     Array(
       0.U -> "b00100".U(5.W),
       1.U -> "b00100".U(5.W),
@@ -193,7 +193,7 @@ class SRT4DividerDataModule(len: Int) extends Module {
       7.U -> "b01000".U(5.W),
     )
   )
-  val mInitPos2 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b01100".U(5.W),
+  val mInitPos2 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b01100".U(5.W))(
     Array(
       0.U -> "b01100".U(5.W),
       1.U -> "b01110".U(5.W),
@@ -410,7 +410,7 @@ class SRT4QDS(len: Int, itn_len: Int) extends Module {
         csa1.io.in(1) := trunc25(remCarryX16)
         csa2.io.in(2) := trunc25(dXq)
       }
-      csa1.io.in(2) := MuxLookup(dForLookup, "b0000000".U, mLookUpTable.minus_m(i))
+      csa1.io.in(2) := MuxLookup(dForLookup, "b0000000".U)(mLookUpTable.minus_m(i))
       csa2.io.in(0) := csa1.io.out(0)
       csa2.io.in(1) := csa1.io.out(1)(5, 0) << 1
       (csa2.io.out(0) + (csa2.io.out(1)(5, 0) << 1))(6)

src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala

@@ -546,7 +546,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
 
   def missCohGen(cmd: UInt, param: UInt, dirty: Bool) = {
     val c = categorize(cmd)
-    MuxLookup(Cat(c, param, dirty), Nothing, Seq(
+    MuxLookup(Cat(c, param, dirty), Nothing)(Seq(
       //(effect param) -> (next)
       Cat(rd, toB, false.B)  -> Branch,
       Cat(rd, toB, true.B)   -> Branch,

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -778,7 +778,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule
   refill.id := req.id
   def missCohGen(cmd: UInt, param: UInt, dirty: Bool) = {
     val c = categorize(cmd)
-    MuxLookup(Cat(c, param, dirty), Nothing, Seq(
+    MuxLookup(Cat(c, param, dirty), Nothing)(Seq(
       //(effect param) -> (next)
       Cat(rd, toB, false.B)  -> Branch,
       Cat(rd, toB, true.B)   -> Branch,
@@ -787,7 +787,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule
       Cat(wi, toT, false.B)  -> Trunk,
       Cat(wi, toT, true.B)   -> Dirty,
       Cat(wr, toT, false.B)  -> Dirty,
-      Cat(wr, toT, true.B)   -> Dirty))
+      Cat(wr, toT, true.B)   -> Dirty).toSeq)
   }
   refill.meta.coh := ClientMetadata(missCohGen(req.cmd, grant_param, isDirty))
   refill.error := error

src/main/scala/xiangshan/cache/mmu/L2TLB.scala

@@ -458,8 +458,7 @@ class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) wi
   }
 
   def outReady(source: UInt, port: Int): Bool = {
-    MuxLookup(source, true.B,
-      (0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready))
+    MuxLookup(source, true.B)((0 until PtwWidth).map(i => i.U -> mergeArb(i).in(port).ready))
   }
 
   // debug info

src/main/scala/xiangshan/cache/mmu/MMUBundle.scala

@@ -209,7 +209,7 @@ class TlbEntry(pageNormal: Boolean, pageSuper: Boolean)(implicit p: Parameters)
     this.tag := {if (pageNormal) Cat(item.entry.tag, OHToUInt(item.pteidx)) else item.entry.tag(sectorvpnLen - 1, vpnnLen - sectortlbwidth)}
     this.asid := asid
     val inner_level = item.entry.level.getOrElse(0.U)
-    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U, Seq(
+    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U)(Seq(
       0.U -> 3.U,
       1.U -> 1.U,
       2.U -> 0.U ))
@@ -341,7 +341,7 @@ class TlbSectorEntry(pageNormal: Boolean, pageSuper: Boolean)(implicit p: Parame
     this.tag := {if (pageNormal) item.entry.tag else item.entry.tag(sectorvpnLen - 1, vpnnLen - sectortlbwidth)}
     this.asid := asid
     val inner_level = item.entry.level.getOrElse(0.U)
-    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U, Seq(
+    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U)(Seq(
                                                         0.U -> 3.U,
                                                         1.U -> 1.U,
                                                         2.U -> 0.U ))
@@ -732,7 +732,7 @@ class PtwEntry(tagLen: Int, hasPerm: Boolean = false, hasLevel: Boolean = false)
 
   def genPPN(vpn: UInt): UInt = {
     if (!hasLevel) ppn
-    else MuxLookup(level.get, 0.U, Seq(
+    else MuxLookup(level.get, 0.U)(Seq(
           0.U -> Cat(ppn(ppn.getWidth-1, vpnnLen*2), vpn(vpnnLen*2-1, 0)),
           1.U -> Cat(ppn(ppn.getWidth-1, vpnnLen), vpn(vpnnLen-1, 0)),
           2.U -> ppn)
@@ -984,7 +984,7 @@ class PtwSectorResp(implicit p: Parameters) extends PtwBundle {
   val af = Bool()
 
   def genPPN(vpn: UInt): UInt = {
-    MuxLookup(entry.level.get, 0.U, Seq(
+    MuxLookup(entry.level.get, 0.U)(Seq(
       0.U -> Cat(entry.ppn(entry.ppn.getWidth-1, vpnnLen * 2 - sectortlbwidth), vpn(vpnnLen*2-1, 0)),
       1.U -> Cat(entry.ppn(entry.ppn.getWidth-1, vpnnLen - sectortlbwidth), vpn(vpnnLen-1, 0)),
       2.U -> Cat(entry.ppn(entry.ppn.getWidth-1, 0), ppn_low(vpn(sectortlbwidth - 1, 0))))

src/main/scala/xiangshan/cache/mmu/TLBStorage.scala

@@ -247,7 +247,7 @@ class TLBFakeFA(
       resp.bits.perm(d).w := pte.perm.w
       resp.bits.perm(d).r := pte.perm.r
 
-      resp.bits.ppn(d) := MuxLookup(level, 0.U, Seq(
+      resp.bits.ppn(d) := MuxLookup(level, 0.U)(Seq(
         0.U -> Cat(ppn(ppn.getWidth-1, vpnnLen*2), vpn_reg(vpnnLen*2-1, 0)),
         1.U -> Cat(ppn(ppn.getWidth-1, vpnnLen), vpn_reg(vpnnLen-1, 0)),
         2.U -> ppn)

src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala

@@ -536,7 +536,7 @@ class MutiLevelPrefetchFilter(implicit p: Parameters) extends XSModule with HasL
     val evict = s1_alloc && (s1_index === i.U)
     l2_pf_req_arb.io.in(i).valid := array(i).can_send_pf() && (array(i).sink === SINK_L2) && !evict
     l2_pf_req_arb.io.in(i).bits.addr := array(i).get_pf_addr()
-    l2_pf_req_arb.io.in(i).bits.source := MuxLookup(array(i).source.value, MemReqSource.Prefetch2L2Unknown.id.U, Seq(
+    l2_pf_req_arb.io.in(i).bits.source := MuxLookup(array(i).source.value, MemReqSource.Prefetch2L2Unknown.id.U)(Seq(
       L1_HW_PREFETCH_STRIDE -> MemReqSource.Prefetch2L2Stride.id.U,
       L1_HW_PREFETCH_STREAM -> MemReqSource.Prefetch2L2Stream.id.U
     ))

src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala

@@ -17,7 +17,8 @@
 package xiangshan.mem
 
 import org.chipsalliance.cde.config.Parameters
-import chisel3.experimental.{DataMirror, requireIsChiselType}
+import chisel3.experimental.requireIsChiselType
+import chisel3.reflect.DataMirror
 import chisel3._
 import chisel3.util._
 import xiangshan._