Memblock: VsegmentUnit's tlb resquest delay 1 cycle & latch vaddr

This commit latch vaddr for merge Dcache's data and delay 1 cycle tlb request for better timing.

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -739,11 +739,12 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     // dtlb
     loadUnits(i).io.tlb <> dtlb_reqs.take(LduCnt)(i)
     if(i == 0 ){ // port 0 assign to vsegmentUnit
-      dtlb_reqs.take(LduCnt)(i).req.valid := loadUnits(i).io.tlb.req.valid || vSegmentUnit.io.dtlb.req.valid
+      val vsegmentDtlbReqValid = vSegmentUnit.io.dtlb.req.valid // segment tlb resquest need to delay 1 cycle
+      dtlb_reqs.take(LduCnt)(i).req.valid := loadUnits(i).io.tlb.req.valid || RegNext(vsegmentDtlbReqValid)
       vSegmentUnit.io.dtlb.req.ready      := dtlb_reqs.take(LduCnt)(i).req.ready
       dtlb_reqs.take(LduCnt)(i).req.bits  := Mux1H(Seq(
-        vSegmentUnit.io.dtlb.req.valid -> vSegmentUnit.io.dtlb.req.bits,
-        loadUnits(i).io.tlb.req.valid -> loadUnits(i).io.tlb.req.bits
+        RegNext(vsegmentDtlbReqValid)     -> RegEnable(vSegmentUnit.io.dtlb.req.bits, vsegmentDtlbReqValid),
+        loadUnits(i).io.tlb.req.valid     -> loadUnits(i).io.tlb.req.bits
       ))
     }
     // pmp

src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala

@@ -104,6 +104,7 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
 
   val maxSegIdx         = instMicroOp.vl - 1.U
   val maxNfields        = instMicroOp.uop.vpu.nf
+  val latchVaddr        = RegInit(0.U(VAddrBits.W))
 
   XSError((segmentIdx > maxSegIdx) && instMicroOpValid, s"segmentIdx > vl, something error!\n")
   XSError((fieldIdx > maxNfields) &&  instMicroOpValid, s"fieldIdx > nfields, something error!\n")
@@ -276,6 +277,11 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
                                             indexStride,
                                             segmentOffset)
   val vaddr                           = baseVaddr + (fieldIdx << alignedType).asUInt + realSegmentOffset
+
+  //latch vaddr
+  when(state === s_tlb_req){
+    latchVaddr := vaddr
+  }
   /**
    * tlb req and tlb resq
    */
@@ -349,7 +355,7 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
   /**
    * merge data for load
    */
-  val cacheData = LookupTree(vaddr(3,0), List(
+  val cacheData = LookupTree(latchVaddr(3,0), List(
     "b0000".U -> io.rdcache.resp.bits.data_delayed(63,    0),
     "b0001".U -> io.rdcache.resp.bits.data_delayed(63,    8),
     "b0010".U -> io.rdcache.resp.bits.data_delayed(63,   16),
@@ -387,15 +393,15 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
     alignedType = alignedType
   )
   val flowData  = genVWdata(splitData, alignedType) // TODO: connect vstd, pass vector data
-  val wmask     = genVWmask(vaddr, alignedType(1, 0)) & Fill(VLENB, segmentActive)
+  val wmask     = genVWmask(latchVaddr, alignedType(1, 0)) & Fill(VLENB, segmentActive)
 
   /**
    * rdcache req, write request don't need to query dcache, because we write element to sbuffer
    */
   io.rdcache.req                    := DontCare
   io.rdcache.req.valid              := state === s_cache_req && FuType.isVLoad(fuType)
   io.rdcache.req.bits.cmd           := MemoryOpConstants.M_XRD
-  io.rdcache.req.bits.vaddr         := vaddr
+  io.rdcache.req.bits.vaddr         := latchVaddr
   io.rdcache.req.bits.mask          := mask
   io.rdcache.req.bits.data          := flowData
   io.rdcache.pf_source              := LOAD_SOURCE.U
@@ -427,7 +433,7 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
   io.sbuffer.bits.vecValid         := state === s_send_data && segmentActive
   io.sbuffer.bits.mask             := wmask
   io.sbuffer.bits.data             := flowData
-  io.sbuffer.bits.vaddr            := vaddr
+  io.sbuffer.bits.vaddr            := latchVaddr
   io.sbuffer.bits.cmd              := MemoryOpConstants.M_XWR
   io.sbuffer.bits.id               := DontCare
   io.sbuffer.bits.addr             := instMicroOp.paddr