vl: convert read vl instruction to a move instrcuction

* using vset module to move vl from vl register to int register
OpenXiangShan · Jun 18, 2024 · 87c5d21 · 87c5d21
1 parent d8a5033
commit 87c5d21
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Showing 3 changed files with 24 additions and 7 deletions.
diff --git a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
@@ -919,11 +919,25 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   io.deq.uopInfo.numOfWB := uopInfoGen.io.out.uopInfo.numOfWB
   io.deq.uopInfo.lmul := uopInfoGen.io.out.uopInfo.lmul
 
+  // for csrr vl instruction, convert to vsetvl
+  val Vl = 0xC20.U
+  val isCsrrVl = FuType.FuTypeOrR(decodedInst.fuType, FuType.csr) && decodedInst.fuOpType === CSROpType.set && inst.CSRIDX === Vl
+  when (isCsrrVl) {
+    decodedInst.srcType(0) := SrcType.no
+    decodedInst.srcType(1) := SrcType.no
+    decodedInst.srcType(2) := SrcType.no
+    decodedInst.srcType(3) := SrcType.no
+    decodedInst.srcType(4) := SrcType.vp
+    decodedInst.lsrc(4) := Vl_IDX.U
+    decodedInst.blockBackward := false.B
+  }
+
   io.deq.decodedInst := decodedInst
   io.deq.decodedInst.rfWen := (decodedInst.ldest =/= 0.U) && decodedInst.rfWen
   // change vlsu to vseglsu when NF =/= 0.U
   io.deq.decodedInst.fuType := Mux1H(Seq(
-    (!FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu)                   ) -> decodedInst.fuType,
+    ( isCsrrVl) -> FuType.vsetfwf.U,
+    (!FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && !isCsrrVl      ) -> decodedInst.fuType,
     ( FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && inst.NF === 0.U || (inst.NF =/= 0.U && (inst.MOP === "b00".U && inst.SUMOP === "b01000".U))) -> decodedInst.fuType,
     // MOP === b00 && SUMOP === b01000: unit-stride whole register store
     // MOP =/= b00                    : strided and indexed store

diff --git a/src/main/scala/xiangshan/backend/fu/FuConfig.scala b/src/main/scala/xiangshan/backend/fu/FuConfig.scala
@@ -369,6 +369,7 @@ object FuConfig {
     piped = true,
     writeVlRf = true,
     writeVType = true,
+    writeIntRf = true,
     latency = CertainLatency(0),
     immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI),
   )

diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
@@ -3,7 +3,7 @@ package xiangshan.backend.fu.wrapper
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import utility.ZeroExt
-import xiangshan.VSETOpType
+import xiangshan.{VSETOpType, CSROpType}
 import xiangshan.backend.decode.Imm_VSETIVLI
 import xiangshan.backend.decode.isa.bitfield.InstVType
 import xiangshan.backend.fu.vector.Bundles.VType
@@ -100,17 +100,19 @@ class VSetRvfWvf(cfg: FuConfig)(implicit p: Parameters) extends VSetBase(cfg) {
   val oldVL = in.data.src(4).asTypeOf(VConfig()).vl
   val res = WireInit(0.U.asTypeOf(VConfig()))
   val vlmax = vsetModule.io.out.vlmax
+  val isReadVl = in.ctrl.fuOpType === CSROpType.set
   res.vl := Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
               Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl))
   res.vtype := vsetModule.io.out.vconfig.vtype
 
-  out.res.data := Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
-                      Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl))
+  out.res.data := Mux(isReadVl, oldVL,
+                    Mux(vsetModule.io.out.vconfig.vtype.illegal, 0.U,
+                      Mux(VSETOpType.isKeepVl(in.ctrl.fuOpType), oldVL, vsetModule.io.out.vconfig.vl)))
 
   if (cfg.writeVlRf) io.vtype.get.bits := vsetModule.io.out.vconfig.vtype
-  if (cfg.writeVlRf) io.vtype.get.valid := io.out.valid
-  if (cfg.writeVlRf) io.vlIsZero.get := res.vl === 0.U
-  if (cfg.writeVlRf) io.vlIsVlmax.get := res.vl === vlmax
+  if (cfg.writeVlRf) io.vtype.get.valid := !isReadVl && io.out.valid
+  if (cfg.writeVlRf) io.vlIsZero.get := !isReadVl && res.vl === 0.U
+  if (cfg.writeVlRf) io.vlIsVlmax.get := !isReadVl && res.vl === vlmax
 
   debugIO.vconfig := res
 }