Vsplit: Parameterised splitting address 128-bits alignment checking

src/main/scala/xiangshan/mem/vector/VSplit.scala

@@ -328,12 +328,14 @@ abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) e
    * Unit-Stride split to one flow or two flow.
    * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two
    */
-  val usLowBitsAddr    = issueBaseAddr(3, 0) + issueUopOffset(3, 0)
-  val usAligned128     = (usLowBitsAddr(3, 0) === 0.U)// addr 128-bit aligned
-  val usSplitMask      = genUSSplitMask(issueByteMask, splitIdx, usLowBitsAddr(3, 0))
-  val usNoSplit        = (usAligned128 || !(usLowBitsAddr(3, 0) +& PopCount(usSplitMask))(4)) && !issuePreIsSplit && (splitIdx === 0.U)// unit-stride uop don't need to split into two flow
+  val usLowBitsAddr    = getCheckAddrLowBits(issueBaseAddr, maxMemByteNum) + getCheckAddrLowBits(issueUopOffset, maxMemByteNum)
+  val usAligned128     = (getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U)// addr 128-bit aligned
+  val usSplitMask      = genUSSplitMask(issueByteMask, splitIdx, getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum))
+  val usNoSplit        = (usAligned128 || !getOverflowBit(getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) +& PopCount(usSplitMask), maxMemByteNum)) &&
+                          !issuePreIsSplit &&
+                          (splitIdx === 0.U)// unit-stride uop don't need to split into two flow
   val usSplitVaddr     = genUSSplitAddr(vaddr, splitIdx)
-  val regOffset        = usLowBitsAddr(3, 0) // offset in 256-bits vd
+  val regOffset        = getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) // offset in 256-bits vd
   XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n")
 
   // data
@@ -399,7 +401,7 @@ abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) e
   XSPerfAccumulate("out_valid",             io.out.valid)
   XSPerfAccumulate("out_fire",              io.out.fire)
   XSPerfAccumulate("out_fire_unitstride",   io.out.fire && !issuePreIsSplit)
-  XSPerfAccumulate("unitstride_vlenAlign",  io.out.fire && !issuePreIsSplit && io.out.bits.vaddr(3, 0) === 0.U)
+  XSPerfAccumulate("unitstride_vlenAlign",  io.out.fire && !issuePreIsSplit && getCheckAddrLowBits(io.out.bits.vaddr, maxMemByteNum) === 0.U)
   XSPerfAccumulate("unitstride_invalid",    io.out.ready && issueValid && !issuePreIsSplit && PopCount(io.out.bits.mask).orR)
 }
 

src/main/scala/xiangshan/mem/vector/VecCommon.scala

@@ -77,6 +77,14 @@ trait HasVLSUParameters extends HasXSParameter with VLSUConstants {
   override val VLEN = coreParams.VLEN
   override lazy val vlmBindexBits = log2Up(coreParams.VlMergeBufferSize)
   override lazy val vsmBindexBits = log2Up(coreParams.VsMergeBufferSize)
+  lazy val maxMemByteNum = 16 // Maximum bytes for a single memory access
+  /**
+   * get addr aligned low bits
+   * @param addr Address to be check
+   * @param width Width for checking alignment
+   */
+  def getCheckAddrLowBits(addr: UInt, width: Int): UInt = addr(log2Up(width) - 1, 0)
+  def getOverflowBit(in: UInt, width: Int): UInt = in(log2Up(width))
   def isUnitStride(instType: UInt) = instType(1, 0) === "b00".U
   def isStrided(instType: UInt) = instType(1, 0) === "b10".U
   def isIndexed(instType: UInt) = instType(0) === "b1".U