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PS2-HW: Fix DMA channel register addresses
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The macro for address of channel 9 was wrongly having the address of
channel 8, fixed it. (Luckily MADR and QWC were unused so we should be
safe)

Thanks to Fireboyd78 for notifying us about this. (Closes #2091)

Also fixed some inconsistencies where some of the DMA channel register
addresses weren't defined for all the bitfields.
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@ssakash
ssakash committed Oct 10, 2017
1 parent af2278c commit 3356c63
Showing 1 changed file with 7 additions and 2 deletions.
9 changes: 7 additions & 2 deletions pcsx2/Hw.h
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Expand Up @@ -275,6 +275,7 @@ enum EERegisterAddresses
D7_CHCR = 0x1000C800, D7_CHCR = 0x1000C800,
D7_MADR = 0x1000C810, D7_MADR = 0x1000C810,
D7_QWC = 0x1000C820, D7_QWC = 0x1000C820,
D7_TADR = 0x1000C830,


SIF2_CHCR = 0x1000C800, SIF2_CHCR = 0x1000C800,
SIF2_MADR = 0x1000C810, SIF2_MADR = 0x1000C810,
Expand All @@ -285,6 +286,8 @@ enum EERegisterAddresses
D8_CHCR = 0x1000D000, D8_CHCR = 0x1000D000,
D8_MADR = 0x1000D010, D8_MADR = 0x1000D010,
D8_QWC = 0x1000D020, D8_QWC = 0x1000D020,
D8_TADR = 0x1000D030,
D8_SADR = 0x1000D080,


fromSPR_CHCR = 0x1000D000, fromSPR_CHCR = 0x1000D000,
fromSPR_MADR = 0x1000D010, fromSPR_MADR = 0x1000D010,
Expand All @@ -294,8 +297,10 @@ enum EERegisterAddresses


//toSPR //toSPR
D9_CHCR = 0x1000D400, D9_CHCR = 0x1000D400,
D9_MADR = 0x1000D010, D9_MADR = 0x1000D410,
D9_QWC = 0x1000D020, D9_QWC = 0x1000D420,
D9_TADR = 0x1000D430,
D9_SADR = 0x1000D480,


toSPR_CHCR = 0x1000D400, toSPR_CHCR = 0x1000D400,
toSPR_MADR = 0x1000D410, toSPR_MADR = 0x1000D410,
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2 comments on commit 3356c63

@gregory38
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Note that some features are not supported by some channels.

@gregory38
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@ssakash Check the EE user manual.

D7_TADR, D8_TADR doesn't seem to exists. If you confirm it, I will suggest to use comment in code rather than constant. Could be a good idea to check all DMA channels :)

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