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Geometry module, link and board mapping updates - 2 #466
Geometry module, link and board mapping updates - 2 #466
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L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
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Hi @jbsauvan - I have now added a realistic input json file (other than the Stage 1 to Stage 2 mapping which is preliminary). |
Thanks @snwebb I quickly updated the geometry tester class for
You can find the tester class in commit jbsauvan@c5a9dd2 Not sure where the issue is, but it seems there is some problem with the |
Thanks @jbsauvan . I found a few issues that contributed to the problem: Firstly there was a one character error where there was a |
I fixed a couple of issues:
The tests are passed in the tester program, although it crashes at the end with the following error:
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This is due to an issue in fetching the number of links in modules at cmssw/L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc Lines 537 to 538 in 47fb05c
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Thank you - I have now added "disconnected modules" (i.e. modules that currently have no lpGBT links) to the json config file. The tester class now runs without errors. |
Thanks @snwebb |
Thanks - I have updated the code to take this into account. |
Hi @snwebb Stage-1 and lpgbt mappingsI have added some checks for the module <-> stage-1 mapping and found some issues [1]. The commit containing these updates is is jbsauvan@61d12bb cmssw/L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc Lines 591 to 600 in 1f37d1a
what is retrieved are the lpgbt numbers within one sector (as stored in the So detids valid for the whole HGCAl should be defined for lpgbts as well as for Stage-1 FPGAs. Same thing for Stage-2 FPGAs, but that's a bit different in that case. Indeed Stage-2 FPGAs are covering two Stage-1 sectors, so they would probably need a different detid scheme compared to Stage-1 FPGAs. Stage-2 mappingCurrently in the json it seems that there is a number of Stage-2 FPGA equal to the TMT period (18). But we actually won't simulate the Time Multiplexing, since virtually all the TMT FPGAs will do the exact same thing but on different events. So I would remove the TMT duplicates in the json. [1]
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L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
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Thanks @jbsauvan |
Hi @snwebb |
Thanks @jbsauvan I have now added the structure to label the links between Stage1 and Stage2 FPGAs (which would anyway be needed I believe), and in this way obtain the mapping between the Stage1 and Stage2 FPGAs. Stage2 FPGAs cover ~half the detector although there are 3 per end-cap (ignoring time multiplexing). Therefore I have kept the sector identifier also for Stage2, where the sector is taken as the one corresponding to the maximum overlap with Stage 1 (i.e. the lower value in phi). The sector for the Stage1 links is defined to be the same one as connected to the Stage1 FPGA (which might be different to the Stage2 FPGA it is connected to). I have also added the direct module->stage-1 maps and associated function. |
L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
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Thanks a lot, I have implemented all of your suggestions. |
L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
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After running some tests, I noticed that the current detid scheme chosen for What can be done is to still use the [1]
[2]
[3] cmssw/DataFormats/DetId/interface/DetId.h Lines 19 to 22 in 9e67c40
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Thanks @jbsauvan for the comments. I have edited the |
L1Trigger/L1THGCal/plugins/geometries/HGCalTriggerGeometryV9Imp3.cc
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Thanks @snwebb |
Thanks a lot for the comments - I've performed the updates to |
Thanks @snwebb |
Hi @snwebb |
Hi @jbsauvan |
Thanks @jbsauvan - I found a bug whereby the layer was being obtained from the incorrect module class. This is now fixed and the links distribution looks more sensible. |
Thanks @snwebb ! |
I've checked and these scintillator modules don't exist in the json file (so they are treated as disconnected - previously each module was hard-coded to have exactly 1 link). This may be expected, as I remember Paul saying that the scintillator section of his original file was filled 'by-hand' since only the silicon mapping was provided to him. |
Do you know how the scintillator modules are defined in the json? Is it the same as in |
Yes the function |
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@snwebb please find here remaining comments on tiny details
#include <iosfwd> | ||
#include "DataFormats/DetId/interface/DetId.h" | ||
#include "DataFormats/ForwardDetId/interface/ForwardSubdetector.h" |
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These includes should not be needed in this file
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The first include can be omitted, but the other two are necessary. I have however moved these to HGCalModuleDetId.h
and HGCalBackendDetId.h
which might make it cleaner/clearer.
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Hi @jbsauvan - thanks for the comments, which I have all implemented. I have also added a new version of |
Thanks @snwebb Now you can:
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Thanks @jbsauvan , that's done. |
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PR description:
Replacement/continuation of #459, after implementation of module rotation class in cms-sw#32684. Note that the changes from PR32684 have been copied here, as they do not currently exist in the PFCal-dev repository.
This adds new functionality to obtain the mapping between modules, lpgbts, and stage 1 and 2 FPGAs.
These are in the form of a `.json' file, which is then read-in and manipulated (json file only an example skeleton at present)
PR validation:
Tested that the code compiles and each function works in isolation.