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Address AArch64 review comments from Nick. #1

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merged 1 commit into from Oct 20, 2021
Merged

Address AArch64 review comments from Nick. #1

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18 changes: 9 additions & 9 deletions src/hotspot/cpu/aarch64/aarch64_sve.ad
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Expand Up @@ -5376,36 +5376,36 @@ instruct vmask_lasttrue(iRegINoSp dst, pReg src, pReg ptmp) %{
ins_pipe(pipe_slow);
%}

instruct vmask_truecount_partial(iRegINoSp dst, pReg src, pRegGov pgtmp, rFlagsReg cr) %{
instruct vmask_truecount_partial(iRegINoSp dst, pReg src, pReg ptmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() < MaxVectorSize);
match(Set dst (VectorMaskTrueCount src));
effect(TEMP pgtmp, KILL cr);
effect(TEMP ptmp, KILL cr);
ins_cost(2 * SVE_COST);
format %{ "vmask_truecount_partial $dst, $src\t# vector mask truecount partial (sve)" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this, $src);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_whilelo_zr_imm(as_PRegister($pgtmp$$reg), size, Matcher::vector_length(this, $src));
__ sve_cntp($dst$$Register, size, as_PRegister($pgtmp$$reg), as_PRegister($src$$reg));
__ sve_whilelo_zr_imm(as_PRegister($ptmp$$reg), size, Matcher::vector_length(this, $src));
__ sve_cntp($dst$$Register, size, as_PRegister($ptmp$$reg), as_PRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vmask_firsttrue_partial(iRegINoSp dst, pReg src, pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
instruct vmask_firsttrue_partial(iRegINoSp dst, pReg src, pReg ptmp1, pReg ptmp2, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() < MaxVectorSize);
match(Set dst (VectorMaskFirstTrue src));
effect(TEMP pgtmp, TEMP ptmp, KILL cr);
effect(TEMP ptmp1, TEMP ptmp2, KILL cr);
ins_cost(3 * SVE_COST);
format %{ "vmask_firsttrue_partial $dst, $src\t# vector mask firsttrue partial (sve)" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this, $src);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_whilelo_zr_imm(as_PRegister($pgtmp$$reg), size,
__ sve_whilelo_zr_imm(as_PRegister($ptmp1$$reg), size,
Matcher::vector_length(this, $src));
__ sve_brkb(as_PRegister($ptmp$$reg), as_PRegister($pgtmp$$reg), as_PRegister($src$$reg), false);
__ sve_cntp($dst$$Register, size, as_PRegister($pgtmp$$reg), as_PRegister($ptmp$$reg));
__ sve_brkb(as_PRegister($ptmp2$$reg), as_PRegister($ptmp1$$reg), as_PRegister($src$$reg), false);
__ sve_cntp($dst$$Register, size, as_PRegister($ptmp1$$reg), as_PRegister($ptmp2$$reg));
%}
ins_pipe(pipe_slow);
%}
Expand Down
18 changes: 9 additions & 9 deletions src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
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Expand Up @@ -3026,36 +3026,36 @@ instruct vmask_lasttrue(iRegINoSp dst, pReg src, pReg ptmp) %{
ins_pipe(pipe_slow);
%}

instruct vmask_truecount_partial(iRegINoSp dst, pReg src, pRegGov pgtmp, rFlagsReg cr) %{
instruct vmask_truecount_partial(iRegINoSp dst, pReg src, pReg ptmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() < MaxVectorSize);
match(Set dst (VectorMaskTrueCount src));
effect(TEMP pgtmp, KILL cr);
effect(TEMP ptmp, KILL cr);
ins_cost(2 * SVE_COST);
format %{ "vmask_truecount_partial $dst, $src\t# vector mask truecount partial (sve)" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this, $src);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_whilelo_zr_imm(as_PRegister($pgtmp$$reg), size, Matcher::vector_length(this, $src));
__ sve_cntp($dst$$Register, size, as_PRegister($pgtmp$$reg), as_PRegister($src$$reg));
__ sve_whilelo_zr_imm(as_PRegister($ptmp$$reg), size, Matcher::vector_length(this, $src));
__ sve_cntp($dst$$Register, size, as_PRegister($ptmp$$reg), as_PRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct vmask_firsttrue_partial(iRegINoSp dst, pReg src, pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
instruct vmask_firsttrue_partial(iRegINoSp dst, pReg src, pReg ptmp1, pReg ptmp2, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() < MaxVectorSize);
match(Set dst (VectorMaskFirstTrue src));
effect(TEMP pgtmp, TEMP ptmp, KILL cr);
effect(TEMP ptmp1, TEMP ptmp2, KILL cr);
ins_cost(3 * SVE_COST);
format %{ "vmask_firsttrue_partial $dst, $src\t# vector mask firsttrue partial (sve)" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this, $src);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
__ sve_whilelo_zr_imm(as_PRegister($pgtmp$$reg), size,
__ sve_whilelo_zr_imm(as_PRegister($ptmp1$$reg), size,
Matcher::vector_length(this, $src));
__ sve_brkb(as_PRegister($ptmp$$reg), as_PRegister($pgtmp$$reg), as_PRegister($src$$reg), false);
__ sve_cntp($dst$$Register, size, as_PRegister($pgtmp$$reg), as_PRegister($ptmp$$reg));
__ sve_brkb(as_PRegister($ptmp2$$reg), as_PRegister($ptmp1$$reg), as_PRegister($src$$reg), false);
__ sve_cntp($dst$$Register, size, as_PRegister($ptmp1$$reg), as_PRegister($ptmp2$$reg));
%}
ins_pipe(pipe_slow);
%}
Expand Down
14 changes: 6 additions & 8 deletions src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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Expand Up @@ -1978,7 +1978,7 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
return count * 2;
}

// Return the number of dwords poped
// Return the number of dwords popped
int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
int words_pushed = 0;
bool use_sve = false;
Expand Down Expand Up @@ -2053,10 +2053,9 @@ int MacroAssembler::push_p(unsigned int bitset, Register stack) {
return 0;
}

const int num_of_regs = PRegisterImpl::number_of_saved_registers;
unsigned char regs[num_of_regs];
unsigned char regs[PRegisterImpl::number_of_saved_registers];
int count = 0;
for (int reg = 0; reg < num_of_regs; reg++) {
for (int reg = 0; reg < PRegisterImpl::number_of_saved_registers; reg++) {
if (1 & bitset)
regs[count++] = reg;
bitset >>= 1;
Expand All @@ -2075,7 +2074,7 @@ int MacroAssembler::push_p(unsigned int bitset, Register stack) {
return total_push_bytes / 8;
}

// Return the number of dwords poped
// Return the number of dwords popped
int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
bool use_sve = false;
int sve_predicate_size_in_slots = 0;
Expand All @@ -2091,10 +2090,9 @@ int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
return 0;
}

const int num_of_regs = PRegisterImpl::number_of_saved_registers;
unsigned char regs[num_of_regs];
unsigned char regs[PRegisterImpl::number_of_saved_registers];
int count = 0;
for (int reg = 0; reg < num_of_regs; reg++) {
for (int reg = 0; reg < PRegisterImpl::number_of_saved_registers; reg++) {
if (1 & bitset)
regs[count++] = reg;
bitset >>= 1;
Expand Down
7 changes: 4 additions & 3 deletions src/hotspot/cpu/aarch64/register_aarch64.hpp
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Expand Up @@ -243,9 +243,10 @@ class PRegisterImpl: public AbstractRegisterImpl {
enum {
number_of_registers = 16,
number_of_governing_registers = 8,
// AArch64 has 8 governing predicate registers, but p7 is used as an
// all-1s register so the predicates to save are from p0 to p6 if we
// don't have non-governing predicate registers support.
// p0-p7 are governing predicates for load/store and arithmetic, but p7 is
// preserved as an all-true predicate in OpenJDK. And since we don't support
// non-governing predicate registers allocation for non-temp register, the
// predicate registers to be saved are p0-p6.
number_of_saved_registers = number_of_governing_registers - 1,
max_slots_per_register = 1
};
Expand Down
8 changes: 5 additions & 3 deletions src/hotspot/cpu/aarch64/vmreg_aarch64.hpp
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Expand Up @@ -39,18 +39,20 @@ inline bool is_PRegister() {
}

inline Register as_Register() {
assert(is_Register(), "must be");
assert( is_Register(), "must be");
// Yuk
return ::as_Register(value() / RegisterImpl::max_slots_per_register);
}

inline FloatRegister as_FloatRegister() {
assert(is_FloatRegister() && is_even(value()), "must be");
assert( is_FloatRegister() && is_even(value()), "must be" );
// Yuk
return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
FloatRegisterImpl::max_slots_per_register);
}

inline PRegister as_PRegister() {
assert(is_PRegister(), "must be");
assert( is_PRegister(), "must be" );
return ::as_PRegister((value() - ConcreteRegisterImpl::max_fpr) /
PRegisterImpl::max_slots_per_register);
}
Expand Down