T4.1 make SPI CS pins be index not mask, plus Franks change to timing

The CS pins on T4.x are not like 3.x in that is you select one by index, not one or more by mask. So changed returned values to be index (1 based) Also while testing I pulled in Frank's change for adding delay after CS pin is logically selected.
PaulStoffregen · Mar 29, 2020 · fc9159a · fc9159a
1 parent 936c2a8
commit fc9159a
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/SPI.cpp b/SPI.cpp
@@ -1341,7 +1341,7 @@ void SPIClass::setClockDivider_noInline(uint32_t clk) {
 			div =0;
 		}
 
-		_ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2);
+		_ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2) | LPSPI_CCR_PCSSCK(div/2);
 
 	} 
 	//Serial.printf("SPI.setClockDivider_noInline CCR:%x TCR:%x\n", _ccr, port().TCR);
@@ -1519,7 +1519,7 @@ const SPIClass::SPI_Hardware_t  SPIClass::spiclass_lpspi4_hardware = {
 	IOMUXC_LPSPI4_SCK_SELECT_INPUT,
 	10, 37, 36, // CS
 	3 | 0x10, 2 | 0x10, 2 | 0x10, 
-	1, 0x2, 0x4,
+	1, 2, 3,
 	0, 0, 0,
 	&IOMUXC_LPSPI4_PCS0_SELECT_INPUT, 0, 0
 };

diff --git a/SPI.h b/SPI.h
@@ -1221,7 +1221,7 @@ class SPIClass { // Teensy 4
 				div =0;
 			}
 
-			_ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2);
+			_ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2) | LPSPI_CCR_PCSSCK(div/2);
 
 		} 
 		//Serial.printf("SPI.beginTransaction CCR:%x TCR:%x\n", _ccr, settings.tcr);