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Merge pull request #16 from yashgupta26/main
Fix issue 15 counter
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module N_bit_sync_counter(x,ud,clk,clr,q,y); | ||
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parameter N = 4; | ||
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input x,ud,clk,clr; | ||
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output reg [N-1:0] q; | ||
output reg y; | ||
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always @ (negedge clk,posedge clr) | ||
if (clr==1) | ||
begin | ||
q<=0; | ||
y<=0; | ||
end | ||
else | ||
if (x == 1) | ||
if (ud==1) {y,q} <= q + 1'b1; | ||
else | ||
{y,q} <= q - 1'b1; | ||
endmodule |
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`timescale 1ns / 1ps | ||
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module N_bit_sync_counter_tb; | ||
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parameter N = 4; | ||
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reg x,ud,clk,clr; | ||
wire [N-1:0] q; | ||
wire y; | ||
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N_bit_sync_counter UUT(x,ud,clk,clr,q,y); | ||
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initial begin | ||
clk = 0; | ||
forever | ||
#5 clk = ~clk ; | ||
end | ||
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initial begin | ||
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#5 clr = 1'b1; | ||
#5 clr = 1'b0; | ||
ud=1'b0; | ||
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x = 1'b1; | ||
end | ||
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initial | ||
begin | ||
$display("\ttime,\tq,\ty"); | ||
$monitor("\t%d,\t%b,\t%b",$time,q,y); | ||
end | ||
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endmodule |