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关于Cache读写、替换、写回 #2

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474208967 opened this issue Feb 25, 2021 · 0 comments

474208967 commented Feb 25, 2021

您好，看了您的实验，很受启发。我想做一个三级缓存的实验，但是先不需要在FPGA实现，只需要在ModelSim上模拟，查了很多资料，关于Verilog实现三级缓存的几乎没有，想问一下在您的工程中没有看到Cache读写、替换、写回等策略的代码呢？

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