new blocks and bitstream

[buddynohair]

Hello,

i try to generate a new custom block called "hard_logic_block" (similar as a DSP-block), which has the same level as club-block from the hierarchy , but it shows me an error.

Besides, i still wanna ask something about Bitstream. I think the FPGA is successfully generated, but i can't find the bitstream file in the output files.

[angl-dev]

Hi @buddynohair , for the first question, I think you're missing a closing parenthesis at the end of the if condition.

As for bitstream file, if you are able to run the simulation and get the test passed message, you should find the bitstream file: examples/target/{design}/{fpga}/{design}.memh.

[buddynohair]

Hallo, Thank you very much, i have found it. Ang Li <notifications@github.com> 于2020年9月8日周二 上午8:33写道：

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Hi @buddynohair <https://github.com/buddynohair> , for the first question, I think you're missing a closing parenthesis at the end of the if condition. As for bitstream file, if you are able to run the simulation and get the test passed message, you should find the bitstream file: examples/target/{design}/{fpga}/{design}.memh. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#11 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AP6XRE6QCAALU62AF7ITPLLSEXF23ANCNFSM4Q45V45Q> .