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i try to generate a new custom block called "hard_logic_block" (similar as a DSP-block), which has the same level as club-block from the hierarchy , but it shows me an error.
Besides, i still wanna ask something about Bitstream. I think the FPGA is successfully generated, but i can't find the bitstream file in the output files.
The text was updated successfully, but these errors were encountered:
Hi @buddynohair , for the first question, I think you're missing a closing parenthesis at the end of the if condition.
As for bitstream file, if you are able to run the simulation and get the test passed message, you should find the bitstream file: examples/target/{design}/{fpga}/{design}.memh.
Hello,
i try to generate a new custom block called "hard_logic_block" (similar as a DSP-block), which has the same level as club-block from the hierarchy , but it shows me an error.
![截屏2020-09-06下午11 18 51](https://user-images.githubusercontent.com/66943123/92335474-7ca2e680-f097-11ea-9905-fedb5853e2e8.png)
![截屏2020-09-06下午11 19 11](https://user-images.githubusercontent.com/66943123/92335478-81679a80-f097-11ea-9c93-dd1db0371ed8.png)
Besides, i still wanna ask something about Bitstream. I think the FPGA is successfully generated, but i can't find the bitstream file in the output files.
The text was updated successfully, but these errors were encountered: