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Handle gates with ctrl_stete=0 #2148

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merged 13 commits into from
May 30, 2024
8 changes: 8 additions & 0 deletions qiskit_aer/backends/aer_compiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -823,6 +823,14 @@ def _assemble_op(
}:
aer_circ.gate(name, qubits, params, [], conditional_reg, aer_cond_expr,
label if label else name)
elif name == "cx_o0":

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Shouldn't we check this for other gates as well? The same would be applicable to cy, cz and other gates (with ctrl_state arg) right?

qubits_0 = [qubits[0]]
aer_circ.gate("x", qubits_0, params, [], conditional_reg, aer_cond_expr,
label if label else "x")
aer_circ.gate("cx", qubits, params, [], conditional_reg, aer_cond_expr,
label if label else "cx")
aer_circ.gate("x", qubits_0, params, [], conditional_reg, aer_cond_expr,
label if label else "x")
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elif name == "measure":
if is_conditional:
aer_circ.measure(qubits, clbits, clbits)
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