Aten vs C10

Dispatching to different device types, architectures, memory layouts, etc.

TensorTypeId

C10/core/TensorTypeId => Assigns an id to each Tensor that is used for dispatching on the right backend implementation.

Example TypeIds are as follows:
UndefinedTensorId = 0,

  // This pool of IDs is not really ordered, but it is merged into
  // the hierarchy for convenience and performance
  CPUTensorId, // PyTorch/Caffe2 supported
  CUDATensorId, // PyTorch/Caffe2 supported
  MKLDNNTensorId, // Caffe2 only
  OpenGLTensorId, // Caffe2 only
  OpenCLTensorId, // Caffe2 only
  IDEEPTensorId, // Caffe2 only
  HIPTensorId, // PyTorch/Caffe2 supported
  SparseHIPTensorId, // PyTorch only
  MSNPUTensorId, // PyTorch only
  XLATensorId, // PyTorch only
  MkldnnCPUTensorId,
  QuantizedCPUTensorId, // PyTorch only
  ComplexCPUTensorId, // PyTorch only
  ComplexCUDATensorId, // PyTorch only

  // Sparse has multi-dispatch with dense; handle it first
  SparseCPUTensorId, // PyTorch only
  SparseCUDATensorId

TensorTypeSet A representation of a set of TensorTypeIds. A tensor may have multiple tensor type ids, e.g., a Variable tensor can also be a CPU tensor; the TensorTypeSet specifies what type ids apply.

Here we overload all the operators like =, and, <<, depending on the type of TensorTypeId

ThreadPool Implementation

Operator Registration

https://github.com/pytorch/pytorch/blob/master/aten/src/ATen/core/op_registration/op_registration.h

Things to care about:

1. Operator
2. Schema
3. Kernel