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rm matvec & furthur optimize performance #71
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Codecov Report
@@ Coverage Diff @@
## master #71 +/- ##
==========================================
+ Coverage 80.51% 80.90% +0.38%
==========================================
Files 8 8
Lines 544 555 +11
==========================================
+ Hits 438 449 +11
Misses 106 106
Continue to review full report at Codecov.
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The register size is too small. Do you have benchmark for the larger size? |
20 qubits Before: BenchmarkTools.Trial:
memory estimate: 688 bytes
allocs estimate: 17
--------------
minimum time: 1.470 ms (0.00% GC)
median time: 1.501 ms (0.00% GC)
mean time: 1.500 ms (0.00% GC)
maximum time: 1.558 ms (0.00% GC)
--------------
samples: 279
evals/sample: 1 after: BenchmarkTools.Trial:
memory estimate: 32 bytes
allocs estimate: 2
--------------
minimum time: 1.379 ms (0.00% GC)
median time: 1.405 ms (0.00% GC)
mean time: 1.407 ms (0.00% GC)
maximum time: 1.489 ms (0.00% GC)
--------------
samples: 282
evals/sample: 1 |
But I don't know why do we need new instructs. Why not fixing the U1 instruction directly? |
GiggleLiu
reviewed
Sep 26, 2020
GiggleLiu
reviewed
Sep 26, 2020
GiggleLiu
reviewed
Sep 26, 2020
GiggleLiu
reviewed
Sep 26, 2020
Co-authored-by: Leo <cacate0129@gmail.com>
Co-authored-by: Leo <cacate0129@gmail.com>
Co-authored-by: Leo <cacate0129@gmail.com>
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this further optimizes the performance of rotation gates.
before:
after: