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Merge 61fa586 into 0c0d38a
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@yodalee
yodalee committed Jan 18, 2015
2 parents 0c0d38a + 61fa586 commit a76b400
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Showing 54 changed files with 198 additions and 196 deletions.
4 changes: 2 additions & 2 deletions qucs/qucs/components/andor4x2.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ QString andor4x2::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString a11 = Ports.at(0)->Connection->Name;
Expand All @@ -133,7 +133,7 @@ QString andor4x2::vhdlCode( int )
QString andor4x2::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/andor4x3.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,7 @@ QString andor4x3::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString a11 = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -156,7 +156,7 @@ QString andor4x3::vhdlCode( int )
QString andor4x3::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/andor4x4.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,7 @@ QString andor4x4::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString a11 = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -168,7 +168,7 @@ QString andor4x4::vhdlCode( int )
QString andor4x4::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString a11 = Ports.at(0)->Connection->Name;
QString a12 = Ports.at(1)->Connection->Name;
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/binarytogrey4bit.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ QString binarytogrey4bit::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString B0 = Ports.at(0)->Connection->Name;
Expand All @@ -130,7 +130,7 @@ QString binarytogrey4bit::vhdlCode( int )
QString binarytogrey4bit::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString B0 = Ports.at(0)->Connection->Name;
QString B1 = Ports.at(1)->Connection->Name;
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/comp_1bit.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ QString comp_1bit::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString X = Ports.at(0)->Connection->Name;
Expand All @@ -113,7 +113,7 @@ QString comp_1bit::verilogCode( int )
QString l="";

QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString X = Ports.at(0)->Connection->Name;
QString Y = Ports.at(1)->Connection->Name;
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/comp_2bit.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@ QString comp_2bit::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString X0 = Ports.at(0)->Connection->Name;
Expand All @@ -125,7 +125,7 @@ QString comp_2bit::verilogCode( int )
QString l="";

QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString X0 = Ports.at(0)->Connection->Name;
QString X1 = Ports.at(1)->Connection->Name;
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/comp_4bit.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ QString comp_4bit::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString X0 = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -154,7 +154,7 @@ QString comp_4bit::verilogCode( int )
QString l="";

QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString X0 = Ports.at(0)->Connection->Name;
QString X1 = Ports.at(1)->Connection->Name;
Expand Down
8 changes: 4 additions & 4 deletions qucs/qucs/components/component.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1079,7 +1079,7 @@ int Component::analyseLine(const QString& Row, int numProps)
s = Row.mid(Row.indexOf('"')+1); // Text (can contain " !!!)
s = s.left(s.length()-1);
if(s.isEmpty()) return -1;
convert2Unicode(s);
misc::convert2Unicode(s);

Texts.append(new Text(i1, i2, s, Color, float(i3),
float(cos(float(i4)*M_PI/180.0)),
Expand Down Expand Up @@ -1368,7 +1368,7 @@ QString GateComponent::vhdlCode(int NumPorts)

if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td;
if(!misc::VHDL_Delay(td, Name)) return td;
s += td;
}

Expand Down Expand Up @@ -1399,7 +1399,7 @@ QString GateComponent::verilogCode(int NumPorts)

if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " " + pp->Connection->Name + " = "; // output port
Expand All @@ -1422,7 +1422,7 @@ QString GateComponent::verilogCode(int NumPorts)

if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " " + Name + " (" + pp->Connection->Name; // output port
Expand Down
24 changes: 12 additions & 12 deletions qucs/qucs/components/componentdialog.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1214,9 +1214,9 @@ void ComponentDialog::slotNumberChanged(const QString&)
QString Unit, tmp;
double x, y, Factor;
if(comboType->currentIndex() == 1) { // logarithmic ?
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
if(y == 0.0) y = x / 10.0;
if(x == 0.0) x = y * 10.0;
Expand All @@ -1225,15 +1225,15 @@ void ComponentDialog::slotNumberChanged(const QString&)
Unit = QString::number(x);
}
else {
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
x = (x - y) / (editNumber->text().toDouble() - 1.0);

QString step = num2str(x);
QString step = misc::num2str(x);

str2num(step, x, Unit, Factor);
misc::str2num(step, x, Unit, Factor);
if(Factor == 1.0)
Unit = "";

Expand All @@ -1251,25 +1251,25 @@ void ComponentDialog::slotStepChanged(const QString& Step)
QString Unit;
double x, y, Factor;
if(comboType->currentIndex() == 1) { // logarithmic ?
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;

x /= y;
str2num(Step, y, Unit, Factor);
misc::str2num(Step, y, Unit, Factor);
y *= Factor;

x = log10(fabs(x)) * y;
}
else {
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;

x -= y;
str2num(Step, y, Unit, Factor);
misc::str2num(Step, y, Unit, Factor);
y *= Factor;

x /= y;
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/d_flipflop.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ QString D_FlipFlop::vhdlCode(int NumPorts)
QString s = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
s += td;
}
s += ";\n";
Expand All @@ -83,7 +83,7 @@ QString D_FlipFlop::verilogCode(int NumPorts)
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!td.isEmpty()) t = " " + td + ";\n";
}

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/dff_SR.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ QString dff_SR::vhdlCode( int )
QString s="";

QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString S = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -130,7 +130,7 @@ QString dff_SR::vhdlCode( int )
QString dff_SR::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/digi_source.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ QString Digi_Source::vhdlCode(int NumPorts)
while(!t.isEmpty()) {
s += Out + State + "';"; // next value for signal

if(!VHDL_Delay(t, Name))
if(!misc::VHDL_Delay(t, Name))
return t; // time has not VHDL format

s += t.replace("after","wait for") + ";\n";
Expand Down Expand Up @@ -165,7 +165,7 @@ QString Digi_Source::verilogCode(int NumPorts)

t = Props.next()->Value.section(';',z,z).trimmed();
while(!t.isEmpty()) {
if(!Verilog_Delay(t, Name))
if(!misc::Verilog_Delay(t, Name))
return t; // time has not VHDL format
s += " " + r + " = " + State + ";\n";
s += " " + t + ";\n";
Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/dmux2to4.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ QString dmux2to4::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString En = Ports.at(0)->Connection->Name;
Expand All @@ -130,7 +130,7 @@ QString dmux2to4::vhdlCode( int )
QString dmux2to4::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/dmux3to8.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,7 @@ QString dmux3to8::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString En = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -155,7 +155,7 @@ QString dmux3to8::vhdlCode( int )
QString dmux3to8::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/dmux4to16.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -147,7 +147,7 @@ QString dmux4to16::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString En = Ports.at(0)->Connection->Name;
Expand Down Expand Up @@ -198,7 +198,7 @@ QString dmux4to16::vhdlCode( int )
QString dmux4to16::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/fa1b.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ QString fa1b::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString A = Ports.at(0)->Connection->Name;
Expand All @@ -110,7 +110,7 @@ QString fa1b::vhdlCode( int )
QString fa1b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/fa2b.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ QString fa2b::vhdlCode( int )
QString s="";

QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString D = Ports.at(0)->Connection->Name;
Expand All @@ -133,7 +133,7 @@ QString fa2b::vhdlCode( int )
QString fa2b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down
4 changes: 2 additions & 2 deletions qucs/qucs/components/gatedDlatch.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ QString gatedDlatch::vhdlCode( int )
QString s="";

QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";

QString D = Ports.at(0)->Connection->Name;
Expand All @@ -111,7 +111,7 @@ QString gatedDlatch::vhdlCode( int )
QString gatedDlatch::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format

QString l = "";

Expand Down

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