verilog models: standard conformance

Mainly, removing misplaced attribute instance unless `insideADMS is
defined.

Now works with both ADMS (Qucsator), modelgen-verilog (Gnucsator), and
possibly others.

src/components/verilog/DLS_1ton.va

@@ -13,12 +13,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module DLS_1ton (Lin, Lout); 
  inout Lin, Lout;
  electrical Lin, Lout;
  electrical n1, n2;
  electrical Vout;
- `define attr(txt) (*txt*)
  parameter real LEVEL = 5 from [1:inf] `attr(info= "voltage level" unit="V");
  parameter real Delay = 1e-9 from [0:inf] `attr(info="time delay" unit="s");
 //

src/components/verilog/DLS_nto1.va

@@ -13,11 +13,17 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module DLS_nto1 (Lin, Lout); 
  inout Lin, Lout;
  electrical Lin, Lout;
  electrical n1, n2;
- `define attr(txt) (*txt*)
  parameter real LEVEL=5 from [1:inf] `attr(info= "voltage level" unit="V");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="time delay" unit="s");
 //

src/components/verilog/EKV26MOS.va

@@ -22,10 +22,12 @@
  `define P(p) (*p*)
  `define PGIVEN(p)	$given(p)
  `define INITIAL_MODEL	@(initial_model)
+ `define attr(txt) (*txt*)
 `else
  `define P(p)
  `define PGIVEN(p)	p
  `define INITIAL_MODEL	@(initial_step)
+ `define attr(txt)
 `endif
 
 `define NMOS	+1
@@ -37,7 +39,6 @@
 electrical Drain, Gate, Source, Bulk;
 // Internal nodes
 electrical Drain_int, Source_int;
-`define attr(txt) (*txt*)
 // Device dimension parameters
  parameter real LEVEL = 1 from [1 : 2]                `attr(info="long = 1, short = 2");
  parameter real L = 0.5e-6 from [0.0 : inf]           `attr(info="length parameter" unit = "m" );
@@ -127,7 +128,7 @@ real con29, con30, con31, con32, con33;
 //
 analog begin
 // Equation initialization
-@(initial_model)
+`INITIAL_MODEL
 begin
   if (`PGIVEN(nmos))
     p_n_MOS = `NMOS;

src/components/verilog/MESFET.va

@@ -12,7 +12,13 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
-// 
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
  module MESFET (Drain, Gate, Source);
  inout Drain, Gate, Source;
 //
@@ -22,7 +28,6 @@ electrical Drain, Gate, Source;
 //
 electrical n1, n2, n3, n4;
 //
- `define attr(txt) (*txt*)
  `define GMIN 1e-12
  `define CTOK 273.15
  `define K1 7.02e-4
@@ -160,7 +165,8 @@ branch (n4, Source) b9;
 //
 analog begin
 //
-Vmax=min(Fc*Vbi, Vmax);
+real Vmax2;
+Vmax2=min(Fc*Vbi, Vmax);
 T1=Tnom+`CTOK;
 T2=$temperature;
 Tr=T2/T1;
@@ -317,7 +323,7 @@ if (QLEVELS==2) begin
 if (QLEVELS==3) begin
 		 Veff1=0.5*( V(b4)+V(b6)+sqrt( pow( V(b4)-V(b6), 2.0)+Vdelta1*Vdelta1 ) );
 		 Vnew =0.5*( Veff1+Vto_T2+sqrt( pow( Veff1-Vto, 2.0 )+Vdelta2*Vdelta2 ) );
-		 if (Vnew>Vmax) Qgs=Cgs_T2*(2*Vbi_T2*(1-sqrt( 1-Vmax/Vbi_T2 ) )+(Vnew-Vmax)/sqrt(1-Vmax/Vbi) );
+		 if (Vnew>Vmax2) Qgs=Cgs_T2*(2*Vbi_T2*(1-sqrt( 1-Vmax2/Vbi_T2 ) )+(Vnew-Vmax2)/sqrt(1-Vmax2/Vbi) );
 		 else Qgs=Cgs_T2*2*Vbi*( 1-sqrt( 1-Vnew/Vbi));
 	        end
 //

src/components/verilog/andor4x2.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module andor4x2 (A11, A12, A21, A22, A31, A32, A41, A42, Y); 
  inout A11, A12, A21, A22, A31, A32, A41, A42, Y;
  electrical A11, A12, A21, A22, A31, A32, A41, A42, Y;
  electrical n1, n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/andor4x3.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module andor4x3 (A11, A12, A13, A21, A22, A23, A31, A32, A33, A41, A42, A43, Y); 
  inout A11, A12, A13, A21, A22, A23, A31, A32, A33, A41, A42, A43, Y;
  electrical A11, A12, A13, A21, A22, A23, A31, A32, A33, A41, A42, A43, Y;
  electrical n1, n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/andor4x4.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module andor4x4 (A11, A12, A13, A14, A21, A22, A23, A24, A31, A32, A33, A34, A41, A42, A43, A44, Y); 
  inout A11, A12, A13, A14, A21, A22, A23, A24, A31, A32, A33, A34, A41, A42, A43, A44, Y;
  electrical A11, A12, A13, A14, A21, A22, A23, A24, A31, A32, A33, A34, A41, A42, A43, A44, Y;
  electrical n1, n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/binarytogrey4bit.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module binarytogrey4bit (B0, B1, B2, B3, G3, G2, G1, G0 );
  inout B0, B1, B2, B3, G3, G2, G1, G0 ;
  electrical B0, B1, B2, B3, G3, G2, G1, G0 ;
  electrical G0n1, G0n2, G1n1, G1n2, G2n1, G2n2, G3n1, G3n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/comp_1bit.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module comp_1bit (X, Y, L, G, E); 
  inout X, Y, L, G, E;
  electrical X, Y, L, G, E;
  electrical Ln1, Ln2, Gn1, Gn2, En1, En2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/comp_2bit.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module comp_2bit (X0, X1, Y0, Y1, L, G, E); 
  inout X0, X1, Y0, Y1, L, G, E;
  electrical X0, X1, Y0, Y1, L, G, E;
  electrical Ln1, Ln2, Gn1, Gn2, En1, En2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/comp_4bit.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module comp_4bit (X0, X1, X2, X3, Y0, Y1, Y2, Y3, L, G, E); 
  inout X0, X1, X2, X3, Y0, Y1, Y2, Y3, L, G, E;
  electrical X0, X1, X2, X3, Y0, Y1, Y2, Y3, L, G, E;
  electrical Ln1, Ln2, Gn1, Gn2, En1, En2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/dff_SR.va

@@ -12,12 +12,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module dff_SR (S, D, CLK, R, QB, QO); 
  inout S, D, CLK, R, QB, QO ;
  electrical S, D, CLK, R, QB, QO;
  electrical n1, n1A, n2, n3, n3A, n4, QA;
 //
- `define attr(txt) (*txt*)
  parameter real TR_H=6 from [1.0:20.0] `attr(info="cross coupled gate transfer function high scaling factor");
  parameter real TR_L=5  from [1.0:20.0] `attr(info="cross coupled gate transfer function low scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="cross coupled gate delay" unit="s");

src/components/verilog/dmux2to4.va

@@ -11,14 +11,20 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module dmux2to4 (EN, A, B, Y3, Y2, Y1, Y0); 
  inout EN, A, B, Y3, Y2, Y1, Y0;
  electrical EN, A, B, Y3, Y2, Y1, Y0;
  electrical Y0n1, Y0n2, Y1n1, Y1n2, Y2n1, Y2n2, Y3n1, Y3n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
- parameter real Delay = 1n from [0: inf] `attr(info="output delay" unit="s");
+ parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //
  real Rd, Cd, VENI, VAI, VBI, IY0, IY1, IY2, IY3;
 //

src/components/verilog/dmux3to8.va

@@ -11,15 +11,21 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module dmux3to8 (EN, A, B, C, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0); 
  inout EN, A, B, C, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
  electrical EN, A, B, C, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
  electrical Y0n1, Y0n2, Y1n1, Y1n2, Y2n1, Y2n2, Y3n1, Y3n2;
  electrical Y4n1, Y4n2, Y5n1, Y5n2, Y6n1, Y6n2, Y7n1, Y7n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
- parameter real Delay = 1n from [0: inf] `attr(info="output delay" unit="s");
+ parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //
  real Rd, Cd, VENI, VAI, VBI, VCI, IY0, IY1, IY2, IY3, IY4, IY5, IY6, IY7;
 //

src/components/verilog/dmux4to16.va

@@ -11,6 +11,13 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module dmux4to16 (EN, A, B, C, D, Y15, Y14, Y13, Y12, Y11, Y10, Y9, Y8, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0); 
  inout EN, A, B, C, D, Y15, Y14, Y13, Y12, Y11, Y10, Y9, Y8, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
  electrical EN, A, B, C, D, Y15, Y14, Y13, Y12, Y11, Y10, Y9, Y8, Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
@@ -19,9 +26,8 @@ module dmux4to16 (EN, A, B, C, D, Y15, Y14, Y13, Y12, Y11, Y10, Y9, Y8, Y7, Y6,
  electrical Y8n1, Y8n2, Y9n1, Y9n2, Y10n1, Y10n2, Y11n1, Y11n2;
  electrical Y12n1, Y12n2, Y13n1, Y13n2, Y14n1, Y14n2, Y15n1, Y15n2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
- parameter real Delay = 1n from [0: inf] `attr(info="output delay" unit="s");
+ parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //
  real Rd, Cd, VENI, VAI, VBI, VCI, VDI, IY0, IY1, IY2, IY3, IY4, IY5, IY6, IY7;
  real IY8, IY9, IY10, IY11, IY12, IY13, IY14, IY15;

src/components/verilog/fa1b.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module fa1b (A, B, CI, CO, S); 
  inout A, B, CI, CO, S;
  electrical A, B,CI, CO, S;
  electrical Sn1, Sn2, COn1, COn2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //

src/components/verilog/fa2b.va

@@ -11,12 +11,18 @@
 //
 `include "disciplines.vams"
 `include "constants.vams"
+
+`ifdef insideADMS
+`define attr(txt) (*txt*)
+`else
+`define attr(txt)
+`endif
+
 module fa2b (D, C, B, A, CI, CO, S1, S0); 
  inout D, C, B, A, CI, CO, S1, S0;
  electrical D, C, B, A, CI, CO, S1, S0;
  electrical S0n1, S0n2, S1n1, S1n2, COn1, COn2;
 //
- `define attr(txt) (*txt*)
  parameter real TR=6 from [1.0:20.0] `attr(info="transfer function high scaling factor");
  parameter real Delay = 1e-9 from [0: inf] `attr(info="output delay" unit="s");
 //