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Merge pull request #6092 from neiljay/pr/add_mips_pic32mx
cpu: Add PIC32MX Support
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MODULE = board | ||
include $(RIOTBASE)/Makefile.base |
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# Put defined MCU peripherals here (in alphabetical order) | ||
FEATURES_PROVIDED += periph_timer | ||
FEATURES_PROVIDED += periph_uart | ||
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# Various other features (if any) | ||
FEATURES_PROVIDED += cpp | ||
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# The board MPU family (used for grouping by the CI system) | ||
FEATURES_MCU_GROUP = mips32r2 |
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export CPU = mips_pic32mx | ||
export CPU_MODEL=p32mx470f512h | ||
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ | ||
export APPDEPS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)/$(CPU_MODEL).S |
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/* | ||
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its | ||
* affiliated group companies. | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
* | ||
*/ | ||
#include <stdio.h> | ||
#include <stdint.h> | ||
#include "periph/uart.h" | ||
#include "bitarithm.h" | ||
#include "board.h" | ||
#include "periph_conf.h" | ||
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extern void dummy(void); | ||
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void board_init(void) | ||
{ | ||
/* | ||
* Setup pin mux for UART3 this is the one connected | ||
* to the mickroBUS | ||
*/ | ||
U3RXREG = 0x2; /*connect pin RPF5 to UART3 RX*/ | ||
RPF4R = 0x1; /*connect pin RPF4 to UART3 TX*/ | ||
PORTFCLR = BIT5 | BIT4; /*set '0' on Porf F pins 4 and 5 */ | ||
TRISFCLR = BIT4; /*set PortF pin 4 for output */ | ||
TRISFSET = BIT5; /*set PortF pin 5 for input */ | ||
ODCFCLR = BIT5 | BIT4; /*set PortF pin 4 and 5 as not open-drain */ | ||
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/* intialise UART used for debug (printf) */ | ||
#ifdef DEBUG_VIA_UART | ||
uart_init(DEBUG_VIA_UART, DEBUG_UART_BAUD, NULL, 0); | ||
#endif | ||
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/* Stop the linker from throwing away the PIC32 config register settings */ | ||
dummy(); | ||
} | ||
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void pm_reboot(void) | ||
{ | ||
/* TODO, note this is needed to get 'default' example to build */ | ||
} |
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/* | ||
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its | ||
* affiliated group companies. | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
* | ||
*/ | ||
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/** | ||
* @defgroup boards_pic32-clicker MikroE PIC32 Clicker | ||
* @ingroup boards | ||
* @brief board configuration for the MikroE PIC32 Clicker | ||
* @details | ||
* see: | ||
* http://www.mikroe.com/pic32/pic32mx-clicker/ | ||
* For more information on the board. | ||
* | ||
* @{ | ||
* | ||
* @file | ||
* @brief board configuration for the MikroE PIC32 Clicker | ||
* | ||
* @author Neil Jones <Neil.Jones@imgtec.com> | ||
*/ | ||
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#ifndef _BOARD_H_ | ||
#define _BOARD_H_ | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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#include "vendor/p32mx470f512h.h" | ||
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/** | ||
* @brief Set how many increments of the count register per uS | ||
* needed by the timer code. | ||
*/ | ||
#define TICKS_PER_US (48) | ||
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/** | ||
* @brief We are using an External Interrupt Controller (all pic32 devices use this mode) | ||
*/ | ||
#define EIC_IRQ (1) | ||
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/** | ||
* @brief Board level initialisation | ||
*/ | ||
void board_init(void); | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* _BOARD_H_ */ | ||
/** @} */ |
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/* | ||
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its | ||
* affiliated group companies. | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
* | ||
*/ | ||
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/** | ||
* @defgroup boards_pic32-clicker MikroE PIC32 Clicker | ||
* @ingroup boards | ||
* @brief peripheral configuration for the MikroE PIC32 Clicker | ||
* @{ | ||
* | ||
* @file | ||
* @brief peripheral configuration for the MikroE PIC32 Clicker | ||
* | ||
* @author Neil Jones <Neil.Jones@imgtec.com> | ||
*/ | ||
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#ifndef _PERIPH_CONF_H_ | ||
#define _PERIPH_CONF_H_ | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @brief The peripheral clock is required for the UART Baud rate calculation | ||
* It is configured by the 'config' registers (see pic32_config_settings.c) | ||
* Note 120MHz is the max F for this device. | ||
*/ | ||
#define PERIPHERAL_CLOCK (96000000) /* Hz */ | ||
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/** | ||
* @brief Timer definitions | ||
* @{ | ||
*/ | ||
#define TIMER_NUMOF (1) | ||
#define TIMER_0_CHANNELS (3) | ||
/** @} */ | ||
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/** | ||
* @brief UART Definitions | ||
* There are 4 UARTS available on this CPU. | ||
* We route debug via UART3 on this board, | ||
* this is the UART connected to the MikroBUS | ||
* | ||
* Note Microchip number the UARTS 1->4 | ||
* @{ | ||
*/ | ||
#define UART_NUMOF (4) | ||
#define DEBUG_VIA_UART (3) | ||
#define DEBUG_UART_BAUD (9600) | ||
/** @} */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif | ||
/** @} */ |
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/* | ||
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its | ||
* affiliated group companies. | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
* | ||
*/ | ||
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#include <stdint.h> | ||
#include "vendor/p32mx470f512h.h" | ||
/* | ||
* DEVCFG3 @ 0x1FC02FF0 | ||
* | ||
* | ||
* USERID | ||
* FSRSSEL 7 Assign IPL 7 to a shadow register set. | ||
* PMDLIWAY 1 | ||
* IOL1WAY 1 | ||
* FUSBIDIO OFF USB USBID Selection Controlled by Port Function | ||
* FVBUSONIO ON VBUSON pin is controlled by the USB module function | ||
*/ | ||
volatile uint32_t _DEVCFG3 __attribute__((used, section(".devcfg3"))) = | ||
0x0 /* unused bits must be 0 */ | ||
| (_DEVCFG3_USERID_MASK & 0xFFFF << _DEVCFG3_USERID_POSITION) | ||
| (_DEVCFG3_FSRSSEL_MASK & 7 << _DEVCFG3_FSRSSEL_POSITION) | ||
| (_DEVCFG3_PMDL1WAY_MASK & 1 << _DEVCFG3_PMDL1WAY_POSITION) | ||
| (_DEVCFG3_IOL1WAY_MASK & 1 << _DEVCFG3_IOL1WAY_POSITION) | ||
| (_DEVCFG3_FUSBIDIO_MASK & 0 << _DEVCFG3_FUSBIDIO_POSITION) | ||
| (_DEVCFG3_FVBUSONIO_MASK & 1 << _DEVCFG3_FVBUSONIO_POSITION); | ||
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/* Note this sets the PLL to 96MHz (8/2 * 24) which is only supported by 3xx | ||
* and 4xx parts and assumes an 8MHz XTAL. | ||
* | ||
* 1xx/2xx/53x/57x only support 50MHz (use 8/2 x 24 / 2 = 48Mhz) | ||
* 5xx/6xx/7xx only support 80Mhz (use 8/2 * 20 = 80MHz). | ||
* | ||
* | ||
* DEVCFG2 @ 0x1FC02FF4 ( | ||
* | ||
* FPLLIDIV DIV_2 System PLL Input Divider 2x Divider | ||
* FPLLMUL 24x System PLL Multiplier PLL Multiply by 24, 8/2 x 24 = 96MHz | ||
* UPLLIDIV DIV_12x USB PLL divider | ||
* UPLLEN OFF USB PLL disabled | ||
* FPLLODIV DIV_1 System PLL Output Clock Divider 1x Divider | ||
*/ | ||
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volatile uint32_t _DEVCFG2 __attribute__ ((used, section(".devcfg2"))) = | ||
0xffffffff /* unused bits must be 1 */ | ||
& (~_DEVCFG2_FPLLIDIV_MASK | 1 << _DEVCFG2_FPLLIDIV_POSITION) | ||
& (~_DEVCFG2_FPLLMUL_MASK | 7 << _DEVCFG2_FPLLMUL_POSITION) | ||
& (~_DEVCFG2_UPLLIDIV_MASK | 7 << _DEVCFG2_UPLLIDIV_POSITION) | ||
& (~_DEVCFG2_UPLLEN_MASK | 0 << _DEVCFG2_UPLLEN_POSITION) | ||
& (~_DEVCFG2_FPLLODIV_MASK | 0 << _DEVCFG2_FPLLODIV_POSITION); | ||
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/* | ||
* DEVCFG1 @ 0x1FC02FF8 | ||
* | ||
* FNOSC PRIPLL Oscillator Selection Bits Primary Osc w/PLL (XT+,HS+,EC+PLL) | ||
* FSOSCEN ON Secondary Oscillator Enable Enabled | ||
* IESO ON Internal/External Switch Over Enabled | ||
* OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled | ||
* FPBDIV DIV_1 Peripheral Clock Divisor Pb_Clk is Sys_Clk/1 | ||
* FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disable, FSCM Disabled | ||
* WDTPS PS2 Watchdog Timer Postscaler 1:2 | ||
* WINDIS OFF Watchdog Timer Window Enable Watchdog Timer is in Non-Window Mode | ||
* FWDTEN OFF Watchdog Timer Enable WDT Disabled (SWDTEN Bit Controls) | ||
* FWDTWINSZ 25% | ||
*/ | ||
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volatile uint32_t _DEVCFG1 __attribute__ ((used, section(".devcfg1"))) = | ||
0xffffffff /* unused bits must be 1 */ | ||
& (~_DEVCFG1_FNOSC_MASK | 3 << _DEVCFG1_FNOSC_POSITION) | ||
& (~_DEVCFG1_FSOSCEN_MASK | 1 << _DEVCFG1_FSOSCEN_POSITION) | ||
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) | ||
& (~_DEVCFG1_POSCMOD_MASK | 1 << _DEVCFG1_POSCMOD_POSITION) | ||
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) | ||
& (~_DEVCFG1_FPBDIV_MASK | 0 << _DEVCFG1_FPBDIV_POSITION) | ||
& (~_DEVCFG1_FCKSM_MASK | 3 << _DEVCFG1_FCKSM_POSITION) | ||
& (~_DEVCFG1_WDTPS_MASK | 1 << _DEVCFG1_WDTPS_POSITION) | ||
& (~_DEVCFG1_WINDIS_MASK | 0 << _DEVCFG1_WINDIS_POSITION) | ||
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) | ||
& (~_DEVCFG1_FWDTWINSZ_MASK | 3 << _DEVCFG1_FWDTWINSZ_POSITION); | ||
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/* | ||
* DEVCFG0 @ 0x1FC02FFC | ||
* | ||
* DEBUG OFF Background Debugger Enable Debugger is disabled | ||
* JTAGEN ON JTAG Enable JTAG Port Enabled | ||
* ICESEL ICS_PGx1 CE/ICD Comm Channel Select Communicate on PGEC1/PGED1 | ||
* PWP OFF Program Flash Write Protect Disable | ||
* BWP OFF Boot Flash Write Protect bit Protection Disabled | ||
* CP OFF Code Protect Protection Disabled | ||
*/ | ||
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volatile uint32_t _DEVCFG0 __attribute__ ((used, section(".devcfg0"))) = | ||
0x7fffffff /* unused bits must be 1 except MSB which is 0 for some odd reason */ | ||
& (~_DEVCFG0_DEBUG_MASK | 3 << _DEVCFG0_DEBUG_POSITION) | ||
& (~_DEVCFG0_JTAGEN_MASK | 1 << _DEVCFG0_JTAGEN_POSITION) | ||
& (~_DEVCFG0_ICESEL_MASK | 3 << _DEVCFG0_ICESEL_POSITION) | ||
& (~_DEVCFG0_PWP_MASK | 0xff << _DEVCFG0_PWP_POSITION) | ||
& (~_DEVCFG0_BWP_MASK | 1 << _DEVCFG0_BWP_POSITION) | ||
& (~_DEVCFG0_CP_MASK | 1 << _DEVCFG0_CP_POSITION); | ||
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/* | ||
* Without a reference to this function from elsewhere LD throws the whole | ||
* compile unit away even though the data is 'volatile' and 'used' !!! | ||
*/ | ||
void dummy(void) | ||
{ | ||
(void)1; | ||
} |
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MODULE = cpu | ||
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USEMODULE += mips_pic32_common | ||
USEMODULE += mips32r2_common | ||
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DIRS += $(RIOTCPU)/mips_pic32_common $(RIOTCPU)/mips32r2_common | ||
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include $(RIOTBASE)/Makefile.base |
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export MEMORY_BASE=0x80000000 | ||
export MEMORY_SIZE=128K | ||
export APP_START=0x80000000 | ||
export ROMABLE = 1 | ||
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include $(RIOTCPU)/Makefile.include.mips_common | ||
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# define build specific options | ||
export CFLAGS += -march=m4k -DSKIP_COPY_TO_RAM | ||
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export USEMODULE += periph | ||
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export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS) | ||
export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mx512_12_128_uhi.ld | ||
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# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!! | ||
export OBJCOPY = objcopy #use system objcopy as toolchain one is broken. | ||
export OFLAGS += -O ihex \ | ||
--change-section-lma .bootflash-0xA0000000 \ | ||
--change-section-lma .exception_vector-0x80000000 \ | ||
--change-section-lma .text-0x80000000 \ | ||
--change-section-lma .init-0x80000000 \ | ||
--change-section-lma .fini-0x80000000 \ | ||
--change-section-lma .eh_frame-0x80000000 \ | ||
--change-section-lma .gcc_except_table-0x80000000 \ | ||
--change-section-lma .jcr-0x80000000 \ | ||
--change-section-lma .ctors-0x80000000 \ | ||
--change-section-lma .dtors-0x80000000 \ | ||
--change-section-lma .rodata-0x80000000 \ | ||
--change-section-lma .data-0x80000000 \ | ||
--change-section-lma .bss-0x80000000 \ | ||
--change-section-lma .startdata-0x80000000 \ |
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