Merge pull request #9437 from biboc/pr/board/samr30-xpro

boards: add samr30-xpro board and samr30 cpu

boards/samr30-xpro/Makefile

@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base

boards/samr30-xpro/Makefile.dep

@@ -0,0 +1,7 @@
+ifneq (,$(filter gnrc_netdev_default netdev_default,$(USEMODULE)))
+  USEMODULE += at86rf212b
+endif
+
+ifneq (,$(filter saul_default,$(USEMODULE)))
+  USEMODULE += saul_gpio
+endif

boards/samr30-xpro/Makefile.features

@@ -0,0 +1,15 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_adc
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m0_2
+
+# samr30 is a specific flavor of saml21
+-include $(RIOTCPU)/saml21/Makefile.features

boards/samr30-xpro/Makefile.include

@@ -0,0 +1,8 @@
+# define the cpu used by the samr30-xpro board (based on saml21)
+export CPU = saml21
+export CPU_MODEL = samr30g18a
+
+# set edbg device type
+EDBG_DEVICE_TYPE = atmel_cm0p
+
+include $(RIOTMAKE)/boards/sam0.inc.mk

boards/samr30-xpro/board.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Baptiste Clenet <bapclenet@gmail.com>
+ *               2018 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_samr30-xpro
+ * @{
+ *
+ * @file        board.c
+ * @brief       Board specific implementations for the Atem SAM R30 Xplained Pro board
+ *
+ * @author      Baptiste Clenet <bapclenet@gmail.com>
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+#include <stdio.h>
+
+#include "board.h"
+#include "cpu.h"
+#include "periph/gpio.h"
+
+void led_init(void);
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+
+    /* initialize the boards LEDs */
+    led_init();
+}
+
+
+/**
+ * @brief Initialize the boards on-board LED
+ */
+void led_init(void)
+{
+    gpio_init(LED0_PIN, GPIO_OUT);
+    gpio_set(LED0_PIN); /* gpio is inverted => clear */
+    gpio_init(LED1_PIN, GPIO_OUT);
+    gpio_set(LED1_PIN); /* gpio is inverted => clear */
+}

boards/samr30-xpro/dist/openocd.cfg

@@ -0,0 +1,2 @@
+source [find target/at91samdXX.cfg]
+$_TARGETNAME configure -rtos auto

boards/samr30-xpro/include/board.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2017 Baptiste Clenet <bapclenet@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup    boards_samr30-xpro Atmel SAM R30 Xplained Pro
+ * @ingroup     boards
+ * @brief       Support for the Atmel SAM R30 Xplained Pro board.
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the Atmel SAM R30 Xplained Pro board.
+ *
+ * @author      Baptiste Clenet <bapclenet@gmail.com>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name NG_AT86RF212B configuration
+ * @{
+ */
+#define AT86RF2XX_PARAM_SPI         SPI_DEV(0)
+#define AT86RF2XX_PARAM_CS          GPIO_PIN(PB, 31)
+#define AT86RF2XX_PARAM_INT         GPIO_PIN(PB, 0)
+#define AT86RF2XX_PARAM_SLEEP       GPIO_PIN(PA, 20)
+#define AT86RF2XX_PARAM_RESET       GPIO_PIN(PB, 15)
+#define AT86RF2XX_PARAM_SPI_CLK     SPI_CLK_5MHZ
+/** @}*/
+
+/**
+ * @name    LED pin definitions and handlers
+ * @{
+ */
+#define LED_PORT                    PORT->Group[0]
+
+#define LED0_PIN                    GPIO_PIN(PA, 18)
+#define LED0_MASK                   (1 << 18)
+#define LED0_ON                     (LED_PORT.OUTCLR.reg = LED0_MASK)
+#define LED0_OFF                    (LED_PORT.OUTSET.reg = LED0_MASK)
+#define LED0_TOGGLE                 (LED_PORT.OUTTGL.reg = LED0_MASK)
+
+#define LED1_PIN                    GPIO_PIN(PA, 19)
+#define LED1_MASK                   (1 << 19)
+#define LED1_ON                     (LED_PORT.OUTCLR.reg = LED1_MASK)
+#define LED1_OFF                    (LED_PORT.OUTSET.reg = LED1_MASK)
+#define LED1_TOGGLE                 (LED_PORT.OUTTGL.reg = LED1_MASK)
+/** @} */
+
+/**
+ * @name    BTN0 (SW0 Button) pin definitions
+ * @{
+ */
+#define BTN0_PORT                   PORT->Group[0]
+#define BTN0_PIN                    GPIO_PIN(PA, 28)
+#define BTN0_MODE                   GPIO_IN_PU
+/** @} */
+
+/**
+ * @brief   Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */

boards/samr30-xpro/include/gpio_params.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2018 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup   boards_samr30-xpro
+ * @{
+ *
+ * @file
+ * @brief     Board specific configuration of direct mapped GPIOs
+ *
+ * @author    Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef GPIO_PARAMS_H
+#define GPIO_PARAMS_H
+
+#include "board.h"
+#include "saul/periph.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief    GPIO pin configuration
+ */
+static const  saul_gpio_params_t saul_gpio_params[] =
+{
+    {
+        .name = "LED(green)",
+        .pin = LED0_PIN,
+        .mode = GPIO_OUT,
+        .flags = SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR,
+    },
+    {
+        .name = "LED(orange)",
+        .pin = LED1_PIN,
+        .mode = GPIO_OUT,
+        .flags = SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR,
+    },
+    {
+        .name = "Button(SW0)",
+        .pin  = BTN0_PIN,
+        .mode = BTN0_MODE,
+        .flags = SAUL_GPIO_INVERTED,
+    },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_PARAMS_H */
+/** @} */

boards/samr30-xpro/include/periph_conf.h

@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2017 Baptiste Clenet <bapclenet@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_samr30-xpro
+ * @{
+ *
+ * @file
+ * @brief       Peripheral MCU configuration for the Atmel SAM R30 Xplained Pro board
+ *
+ * @author      Baptiste Clenet <bapclenet@gmail.com>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   GCLK reference speed
+ */
+#define CLOCK_CORECLOCK     (16000000U)
+
+/**
+ * @name    Timer peripheral configuration
+ * @{
+ */
+#define TIMER_NUMOF        (1U)
+#define TIMER_0_EN         1
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV        TC0->COUNT32
+#define TIMER_0_CHANNELS   1
+#define TIMER_0_MAX_VALUE  (0xffffffff)
+#define TIMER_0_ISR        isr_tc0
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {    /* Virtual COM Port */
+        .dev      = &SERCOM0->USART,
+        .rx_pin   = GPIO_PIN(PA,5),
+        .tx_pin   = GPIO_PIN(PA,4),
+        .mux      = GPIO_MUX_D,
+        .rx_pad   = UART_PAD_RX_1,
+        .tx_pad   = UART_PAD_TX_0,
+        .flags    = UART_FLAG_NONE,
+        .gclk_src = GCLK_PCHCTRL_GEN_GCLK0
+    }
+};
+
+/* interrupt function name mapping */
+#define UART_0_ISR          isr_sercom0
+
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name    SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = &(SERCOM4->SPI),
+        .miso_pin = GPIO_PIN(PC, 19),
+        .mosi_pin = GPIO_PIN(PB, 30),
+        .clk_pin  = GPIO_PIN(PC, 18),
+        .miso_mux = GPIO_MUX_F,
+        .mosi_mux = GPIO_MUX_F,
+        .clk_mux  = GPIO_MUX_F,
+        .miso_pad = SPI_PAD_MISO_0,
+        .mosi_pad = SPI_PAD_MOSI_2_SCK_3
+    }
+};
+
+#define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+/**
+ * @name    I2C configuration
+ * @{
+ */
+static const i2c_conf_t i2c_config[] = {
+    {
+        .dev      = &(SERCOM1->I2CM),
+        .speed    = I2C_SPEED_NORMAL,
+        .scl_pin  = GPIO_PIN(PA, 17),
+        .sda_pin  = GPIO_PIN(PA, 16),
+        .mux      = GPIO_MUX_C,
+        .gclk_src = GCLK_PCHCTRL_GEN_GCLK0,
+        .flags    = I2C_FLAG_NONE
+     }
+};
+#define I2C_NUMOF          (sizeof(i2c_config) / sizeof(i2c_config[0]))
+/** @} */
+
+/**
+ * @name    RTC configuration
+ * @{
+ */
+#define RTC_NUMOF                               (1)
+#define EXTERNAL_OSC32_SOURCE                   1
+#define INTERNAL_OSC32_SOURCE                   0
+#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE     0
+/** @} */
+
+/**
+ * @name    RTT configuration
+ * @{
+ */
+#define RTT_FREQUENCY                           (32768U)
+#define RTT_MAX_VALUE                           (0xffffffffU)
+#define RTT_NUMOF                               (1)
+/** @} */
+
+/**
+ * @name ADC Configuration
+ * @{
+ */
+#define ADC_NUMOF                               (5U)
+
+/* ADC 0 Default values */
+#define ADC_0_CLK_SOURCE                        0 /* GCLK_GENERATOR_0 */
+#define ADC_0_PRESCALER                         ADC_CTRLB_PRESCALER_DIV256
+
+static const adc_conf_chan_t adc_channels[] = {
+    /* port, pin, muxpos */
+    {GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS(ADC_INPUTCTRL_MUXPOS_AIN6)}, /* EXT1, pin 3 */
+    {GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS(ADC_INPUTCTRL_MUXPOS_AIN7)}, /* EXT1, pin 4 */
+    {GPIO_PIN(PA, 10), ADC_INPUTCTRL_MUXPOS(ADC_INPUTCTRL_MUXPOS_AIN18)},
+    {GPIO_PIN(PA, 11), ADC_INPUTCTRL_MUXPOS(ADC_INPUTCTRL_MUXPOS_AIN19)},
+    {GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS(ADC_INPUTCTRL_MUXPOS_AIN0)}
+};
+
+#define ADC_0_NEG_INPUT                         ADC_INPUTCTRL_MUXNEG(0x18u)
+#define ADC_0_REF_DEFAULT                       ADC_REFCTRL_REFSEL_INTVCC2
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */

cpu/sam0_common/Makefile.include

@@ -2,7 +2,7 @@
 CFLAGS += -DCPU_FAM_$(shell echo $(CPU_FAM) | tr 'a-z-' 'A-Z_')
 
 # Set ROM and RAM lengths according to CPU model
-ifneq (,$(filter samd21g18a samd21j18a saml21j18b saml21j18a samr21g18a,$(CPU_MODEL)))
+ifneq (,$(filter samd21g18a samd21j18a saml21j18b saml21j18a samr21g18a samr30g18a,$(CPU_MODEL)))
   ROM_LEN ?= 0x40000
   RAM_LEN ?= 0x8000
 endif