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Merge pull request #4932 from haukepetersen/opt_f1_timer
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cpu/stm32f1: reworked timer implementation
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@PeterKietzmann
PeterKietzmann committed Mar 3, 2016
2 parents 3f99028 + 1c3bd7a commit 2f0901b
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Showing 13 changed files with 203 additions and 446 deletions.
5 changes: 5 additions & 0 deletions boards/fox/include/board.h
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Expand Up @@ -33,6 +33,11 @@
extern "C" {
#endif

/**
* @name Tell the xtimer that we use a 16-bit peripheral timer
*/
#define XTIMER_MASK (0xffff0000)

/**
* @name Define the interface to the AT86RF231 radio
*
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43 changes: 12 additions & 31 deletions boards/fox/include/periph_conf.h
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Expand Up @@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand All @@ -45,37 +47,16 @@ extern "C" {
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_FREQ (CLOCK_CORECLOCK)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0

/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_CHANNELS 4
#define TIMER_1_FREQ (CLOCK_CORECLOCK)
#define TIMER_1_MAX_VALUE (0xffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
static const timer_conf_t timer_config[] = {
/* device, APB bus, rcc_bit */
{ TIM2, APB1, RCC_APB1ENR_TIM2EN, TIM2_IRQn },
{ TIM3, APB1, RCC_APB1ENR_TIM3EN, TIM3_IRQn }
};

#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim3

#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
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5 changes: 5 additions & 0 deletions boards/iotlab-m3/include/board.h
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Expand Up @@ -42,6 +42,11 @@ extern "C" {
#endif
/** @} */

/**
* @name Tell the xtimer that we use a 16-bit peripheral timer
*/
#define XTIMER_MASK (0xffff0000)

/**
* @name Define the interface to the AT86RF231 radio
*
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43 changes: 12 additions & 31 deletions boards/iotlab-m3/include/periph_conf.h
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Expand Up @@ -20,6 +20,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand All @@ -46,37 +48,16 @@ extern "C" {
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_FREQ (CLOCK_CORECLOCK)
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0

/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_CHANNELS 4
#define TIMER_1_FREQ (CLOCK_CORECLOCK)
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
static const timer_conf_t timer_config[] = {
/* device, APB bus, rcc_bit */
{ TIM2, APB1, RCC_APB1ENR_TIM2EN, TIM2_IRQn },
{ TIM3, APB1, RCC_APB1ENR_TIM3EN, TIM3_IRQn }
};

#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim3

#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
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18 changes: 7 additions & 11 deletions boards/nucleo-f103/include/board.h
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Expand Up @@ -35,6 +35,13 @@ extern "C" {
*/
#define STDIO UART_DEV(1)

/**
* @name xtimer configuration
*/
#define XTIMER_MASK (0xffff0000)
#define XTIMER_BACKOFF 5
/** @} */

/**
* @name LED pin definitions
* @{
Expand Down Expand Up @@ -66,17 +73,6 @@ extern "C" {
#define BUTTON_USER_GPIO GPIO_PIN(PORT_C, 13)
/** @} */

/**
* @name xtimer configuration
* @{
*/
#define XTIMER TIMER_0
#define XTIMER_CHAN 0
#define XTIMER_SHIFT 0
#define XTIMER_MASK 0 /* llt 32-bit since combined */
#define XTIMER_BACKOFF 5
/** @} */

/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
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41 changes: 12 additions & 29 deletions boards/nucleo-f103/include/periph_conf.h
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Expand Up @@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand Down Expand Up @@ -47,35 +49,16 @@ extern "C" {
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_1_EN 0

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_FREQ (CLOCK_CORECLOCK)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0

/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_FREQ (CLOCK_CORECLOCK)
#define TIMER_1_MAX_VALUE (0xffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
static const timer_conf_t timer_config[] = {
/* device, APB bus, rcc_bit */
{ TIM2, APB1, RCC_APB1ENR_TIM2EN, TIM2_IRQn },
{ TIM3, APB1, RCC_APB1ENR_TIM3EN, TIM3_IRQn }
};

#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim3

#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
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5 changes: 5 additions & 0 deletions boards/spark-core/include/board.h
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Expand Up @@ -35,6 +35,11 @@
*/
#define LOCATION_VTABLE (0x08005000)

/**
* @name Tell the xtimer that we use a 16-bit peripheral timer
*/
#define XTIMER_MASK (0xffff0000)

/**
* @name LED pin definitions
* @{
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26 changes: 11 additions & 15 deletions boards/spark-core/include/periph_conf.h
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Expand Up @@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_

#include "periph_cpu.h"

#ifdef __cplusplus
extern "C" {
#endif
Expand All @@ -45,22 +47,16 @@
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
static const timer_conf_t timer_config[] = {
/* device, APB bus, rcc_bit */
{ TIM2, APB1, RCC_APB1ENR_TIM2EN, TIM2_IRQn },
{ TIM3, APB1, RCC_APB1ENR_TIM3EN, TIM3_IRQn }
};

#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim3

/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_FREQ (CLOCK_CORECLOCK)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */

/**
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8 changes: 8 additions & 0 deletions cpu/stm32_common/include/periph_cpu_common.h
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Expand Up @@ -39,6 +39,14 @@ extern "C" {
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */

/**
* @brief Available peripheral buses
*/
enum {
APB1,
APB2
};

#ifdef __cplusplus
}
#endif
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20 changes: 20 additions & 0 deletions cpu/stm32f1/include/periph_cpu.h
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Expand Up @@ -43,6 +43,16 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)

/**
* @brief All timers for the STM32F1 have 4 CC channels
*/
#define TIMER_CHANNELS (4U)

/**
* @brief All timers have a width of 16-bit
*/
#define TIMER_MAXVAL (0xffff)

/**
* @brief Override values for pull register configuration
* @{
Expand Down Expand Up @@ -91,6 +101,16 @@ typedef enum {
GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */
} gpio_af_out_t;

/**
* @brief Timer configuration
*/
typedef struct {
TIM_TypeDef *dev; /**< timer device */
uint8_t bus; /**< APBx bus the timer is clock from */
uint8_t rcc_bit; /**< corresponding bit in the RCC register */
uint8_t irqn; /**< global IRQ channel */
} timer_conf_t;

/**
* @brief Configure the alternate function for the given pin
*
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5 changes: 1 addition & 4 deletions cpu/stm32f1/include/stm32f103xb.h
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Expand Up @@ -531,10 +531,7 @@ typedef struct
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t CCR[4]; /*!< TIM capture/compare register 1-4, Address offset: 0x34 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Expand Down
5 changes: 1 addition & 4 deletions cpu/stm32f1/include/stm32f103xe.h
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Expand Up @@ -655,10 +655,7 @@ typedef struct
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t CCR[4]; /*!< TIM capture/compare register 1-4, Address offset: 0x34 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Expand Down

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