cpu/sam3: added RTT driver

boards/arduino-due/Makefile.features

@@ -5,6 +5,7 @@ FEATURES_PROVIDED += periph_dac
 FEATURES_PROVIDED += periph_gpio
 FEATURES_PROVIDED += periph_hwrng
 FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart

boards/arduino-due/include/periph_conf.h

@@ -35,6 +35,9 @@ extern "C" {
 #define CLOCK_CORECLOCK     (84000000UL)
 /* external oscillator clock */
 #define CLOCK_EXT_OSC       (12000000UL)
+/* enable external low-speed oscillator */
+#define CLOCK_SCLK_XTAL     (1)
+
 /* define PLL configuration
  *
  * The values must fulfill this equation:
@@ -62,6 +65,14 @@ static const timer_conf_t timer_config[] = {
 #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
+/**
+ * @name    RTT configuration
+ * @{
+ */
+#define RTT_NUMOF           (1)
+#define RTT_FREQUENCY       (1U)        /* configured to 1Hz */
+/** @} */
+
 /**
  * @name    UART configuration
  * @{

cpu/sam3/cpu.c

@@ -29,6 +29,11 @@
 #define MORKEY              (0x37)
 /** @} */
 
+/**
+ * @brief   Key for writing the SUPC control register
+ */
+#define SUPCKEY             (0xa5)
+
 /**
  * @brief   Start-up time for external crystal (will be multiplied by 8)
  */
@@ -90,6 +95,14 @@ void cpu_init(void)
     /* wait for master clock to be ready */
     while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
 
+    /* setup the SCLK: switch to external oscillator if enabled */
+#if CLOCK_SCSLK_XTAL
+    /* enable external oscillator */
+    SUPC->SUPC_CR = (SUPC_CR_KEY(SUPCKEY) | SUPC_CR_XTALSEL);
+    while (!(SUPC->SUPC_OSCSEL & SUPC_SR_OSCSEL)) {}
+
+#endif
+
     /* trigger static peripheral initialization */
     periph_init();
 }

cpu/sam3/include/periph_cpu.h

@@ -28,6 +28,11 @@
 extern "C" {
 #endif
 
+/**
+ * @brief   The low frequency (slow) clock is always running with 32.768kHz
+ */
+#define CLOCK_SCLK          (32768U)
+
 /**
  * @brief Overwrite the default gpio_t type definition
  */
@@ -70,6 +75,11 @@ typedef uint32_t gpio_t;
  */
 #define TIMER_CHANNELS      (3)
 
+/**
+ * @brief   The RTT width is fixed to 32-bit
+ */
+#define RTT_MAX_VALUE       (0xffffffff)
+
 /**
  * @brief   Generate GPIO mode bitfields
  *

cpu/sam3/periph/rtt.c

@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2017 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_sam3
+ * @ingroup     drivers_periph_rtt
+ *
+ * @note        The hardware RTT unit does neither support overflow interrupts
+ *              nor setting the counter value. For this, this RTT driver does
+ *              not implement those functions.
+ * @{
+ *
+ * @file
+ * @brief       Low-level RTT driver implementation
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "periph/rtt.h"
+
+#define ENABLE_DEBUG        (1)
+#include "debug.h"
+
+static struct {
+    rtt_cb_t cb;
+    void *arg;
+} isr_ctx;
+
+void rtt_init(void)
+{
+    /* enable RTT module */
+    rtt_poweron();
+    /* configure and apply the pre-scaler */
+    uint16_t pre = (CLOCK_SCLK / RTT_FREQUENCY);
+    RTT->RTT_MR = RTT_MR_RTPRES(pre);
+    RTT->RTT_MR |= RTT_MR_RTTRST;
+    DEBUG("[rtt] setting prescaler to %i\n", (int)pre);
+    /* configure NVIC line */
+    NVIC_EnableIRQ(RTT_IRQn);
+}
+
+uint32_t rtt_get_counter(void)
+{
+    return RTT->RTT_VR;
+}
+
+void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
+{
+    /* cancel any existing alarm */
+    RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+    /* set new alarm */
+    isr_ctx.cb  = cb;
+    isr_ctx.arg = arg;
+    RTT->RTT_AR = alarm;
+    DEBUG("[rtt] set new alarm to trigger at %u\n", (unsigned)alarm);
+    /* (re-)enable the alarm */
+    RTT->RTT_MR |= RTT_MR_ALMIEN;
+}
+
+uint32_t rtt_get_alarm(void)
+{
+    if (RTT->RTT_MR & RTT_MR_ALMIEN) {
+        return RTT->RTT_AR;
+    }
+    return 0;
+}
+
+void rtt_clear_alarm(void)
+{
+    RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+}
+
+void rtt_poweron(void)
+{
+    PMC->PMC_PCER0 |= (1 << ID_RTT);
+}
+
+void rtt_poweroff(void)
+{
+    PMC->PMC_PCER0 &= ~(1 << ID_RTT);
+}
+
+void isr_rtt(void)
+{
+    uint32_t state = RTT->RTT_SR;       /* this clears all pending flags */
+    DEBUG("[rtt] ISR: state is 0x%08x\n", (int)state);
+    if (state & RTT_SR_ALMS) {
+        RTT->RTT_MR &= ~(RTT_MR_ALMIEN);
+        isr_ctx.cb(isr_ctx.arg);
+    }
+
+    cortexm_isr_end();
+}