cpu: efm32_common + ef32mg1p: replace with generalized efm32 cpu

cpu/efm32_common/Makefile → cpu/efm32/Makefile

@@ -1,7 +1,6 @@
-# define the module that is build
-MODULE = efm32_common
+MODULE = cpu
 
 # add a list of subdirectories, that should also be build
-DIRS = periph
+DIRS = periph families/$(EFM32_FAMILY) $(RIOTCPU)/cortexm_common
 
 include $(RIOTBASE)/Makefile.base

cpu/efm32_common/Makefile.dep → cpu/efm32/Makefile.dep

@@ -1,7 +1,7 @@
 ifneq (,$(filter periph_rtc,$(USEMODULE)))
-  USEMODULE += periph_rtc_series$(CPU_SERIES)
+  USEMODULE += periph_rtc_series$(EFM32_SERIES)
 endif
 
 ifneq (,$(filter periph_rtt,$(USEMODULE)))
-  USEMODULE += periph_rtt_series$(CPU_SERIES)
+  USEMODULE += periph_rtt_series$(EFM32_SERIES)
 endif

cpu/efm32_common/Makefile.features → cpu/efm32/Makefile.features

@@ -1,3 +1,7 @@
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_flashpage
 FEATURES_PROVIDED += periph_pm
+
+ifeq (1,$(EFM32_TNRG))
+  FEATURES_PROVIDED += periph_hwrng
+endif

cpu/efm32/Makefile.include

@@ -0,0 +1,34 @@
+include $(RIOTCPU)/efm32/efm32-info.mk
+
+export CPU_ARCH = $(EFM32_ARCHITECTURE)
+export CPU_FAM = $(EFM32_FAMILY)
+
+# the em_device.h header requires a global define with the cpu model
+export CFLAGS += -D$(shell echo $(CPU_MODEL) | tr 'a-z' 'A-Z')
+
+# include Gecko SDK package
+USEPKG += gecko_sdk
+
+# CMSIS-DSP is needed for arm_math.h on Cortex-M0+ architectures
+ifeq ($(CPU_ARCH),cortex-m0plus)
+  USEPKG += cmsis-dsp
+endif
+
+# include common periph module
+USEMODULE += periph_common
+
+# include layered power management
+USEMODULE += pm_layered
+
+# include vendor device headers
+INCLUDES += -I$(RIOTCPU)/efm32/families/$(EFM32_FAMILY)/include/vendor
+
+# include cortexm_common
+LINKER_SCRIPT = cortexm.ld
+
+ROM_START_ADDR = $(EFM32_FLASH_START)
+ROM_LEN = $(EFM32_FLASH_SIZE)
+RAM_START_ADDR = $(EFM32_SRAM_START)
+RAM_LEN = $(EFM32_SRAM_SIZE)
+
+include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/efm32_common/cpu.c → cpu/efm32/cpu.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_efm32_common
+ * @ingroup     cpu_efm32
  * @{
  *
  * @file

cpu/efm32/doc.txt

@@ -0,0 +1,66 @@
+/**
+ * @defgroup        cpu_efm32 Silicon Labs EFM32/EFR32/EZR32
+ * @ingroup         cpu
+ * @brief           Implementation of Silicon Labs's EFM32/EFR32/EZR32 MCUs
+ *
+ * This module contains all code and definitions for the Silicon Labs
+ * EFM32/EFR32/EZR32 MCUs. It uses the Gecko SDK (vendor library) for the
+ * peripheral drivers.
+ *
+ *
+ * Supported Peripherals
+ * =====================
+ *
+ * The following peripherals are supported (depends on microcontroller):
+ *   - ADC
+ *   - CPUID
+ *   - DAC
+ *   - Flash page
+ *   - GPIO
+ *   - HW RNG
+ *   - I2C
+ *   - Power Management
+ *   - PWM
+ *   - RTC
+ *   - RTT
+ *   - SPI
+ *   - Timer
+ *   - UART (including low-power)
+ *
+ *
+ * Clock Configuration
+ * ===================
+ *
+ * By default the microcontroller will run on the internal RC-oscillator. If
+ * an external crystal is available, you can configure it to use by setting
+ * `CLOCK_HF=cmuSelect_HFXO`. The same applies for `CLOCK_LFA`, `CLOCK_LFB` and
+ * `CLOCK_LFE` using `cmuSelect_LFXO`.
+ *
+ * If the internal RC-oscillator is not used, it will be disabled.
+ *
+ * Refer to the reference manual of the specific microcontroller for the
+ * specifics.
+ *
+ *
+ * EMU and CMU Configuration
+ * =========================
+ *
+ * The Energy Management Unit (EMU) and Clock Management Unit (CMU) are
+ * initialized using default values provided by the Gecko SDK. You can override
+ * any of the following defaults to use other values:
+ *
+ *   - `CMU_HFXOINIT`
+ *   - `CMU_LFXOINIT`
+ *   - `EMU_DCDCINIT`
+ *   - `EMU_EM23INIT`
+ *   - `EMU_EM4INIT`
+ *
+ * Refer to the Gecko SDK for more information about these values.
+ *
+ *
+ * Low-power Configuration
+ * =======================
+ *
+ * The EFM32/EFR32/EZR32 MCUs have support for low-power peripherals. Support
+ * is enabled by default, but can be disabled by setting LOW_POWER_ENABLED=0.
+ */

cpu/efm32/efm32-info.mk

@@ -0,0 +1,27 @@
+# Find the header file that should exist if the CPU is supported.
+EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/*/include/vendor/$(CPU_MODEL).h)
+
+ifeq (,$(EFM32_HEADER))
+  $(error Header file for $(CPU_MODEL) is missing)
+endif
+
+# Lookup up CPU information using grep.
+EFM32_INFO = $(shell grep $(CPU_MODEL) $(shell dirname $(EFM32_HEADER))/../../cpus.txt)
+
+ifeq (,$(EFM32_INFO))
+  $(error Unable to read CPU information for $(CPU_MODEL))
+endif
+
+# Export variables to use in this build.
+export EFM32_FAMILY = $(word 2, $(EFM32_INFO))
+export EFM32_SERIES = $(word 3, $(EFM32_INFO))
+export EFM32_ARCHITECTURE = $(word 4, $(EFM32_INFO))
+
+export EFM32_FLASH_START = $(word 5, $(EFM32_INFO))
+export EFM32_FLASH_SIZE = $(word 6, $(EFM32_INFO))
+export EFM32_SRAM_START = $(word 7, $(EFM32_INFO))
+export EFM32_SRAM_SIZE = $(word 8, $(EFM32_INFO))
+
+export EFM32_CRYPTO = $(word 9, $(EFM32_INFO))
+export EFM32_TRNG = $(word 10, $(EFM32_INFO))
+export EFM32_RADIO = $(word 11, $(EFM32_INFO))

cpu/efm32/families/efr32mg1p/Makefile

@@ -0,0 +1,6 @@
+MODULE = cpu
+
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += vectors.c
+
+include $(RIOTBASE)/Makefile.base

cpu/efm32/families/efr32mg1p/cpus.txt

@@ -0,0 +1,27 @@
+# This file is automatically generated, and should not be changed. There is
+# propbably little reason to edit this file anyway, since it should already
+# contain all information for the EFR32MG1P family of CPUs.
+
+# The intended usage is to grep for the exact model name, and split by spaces
+# to get the required information.
+
+# CPU - Family - Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
+efr32mg1p632f256gm32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p132f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p233f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p132f256im32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p232f256im32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p133f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p232f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p732f256im32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p232f256gj43 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p232f256gm32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p231f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p732f256gm32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p232f256im48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p132f256im48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p632f256im32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p131f256gm48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p132f256gm32 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p233f256im48 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1
+efr32mg1p132f256gj43 efr32mg1p 1 cortex-m4f 0x00000000 0x00040000 0x20000000 0x00007c00 1 0 1

cpu/efr32mg1p/include/vendor/em_device.h → cpu/efm32/families/efr32mg1p/include/vendor/em_device.h

@@ -49,16 +49,68 @@ extern "C" {
 #ifndef EM_DEVICE_H
 #define EM_DEVICE_H
 
-#if defined(EFR32MG1P132F256GM48)
-#include "efr32mg1p132f256gm48.h"
+#if defined(EFR32MG1P131F256GM48)
+#include "efr32mg1p131f256gm48.h"
+
+#elif defined(EFR32MG1P132F256GJ43)
+#include "efr32mg1p132f256gj43.h"
 
 #elif defined(EFR32MG1P132F256GM32)
 #include "efr32mg1p132f256gm32.h"
 
+#elif defined(EFR32MG1P132F256GM48)
+#include "efr32mg1p132f256gm48.h"
+
+#elif defined(EFR32MG1P132F256IM32)
+#include "efr32mg1p132f256im32.h"
+
+#elif defined(EFR32MG1P132F256IM48)
+#include "efr32mg1p132f256im48.h"
+
+#elif defined(EFR32MG1P133F256GM48)
+#include "efr32mg1p133f256gm48.h"
+
+#elif defined(EFR32MG1P231F256GM48)
+#include "efr32mg1p231f256gm48.h"
+
+#elif defined(EFR32MG1P232F256GJ43)
+#include "efr32mg1p232f256gj43.h"
+
+#elif defined(EFR32MG1P232F256GM32)
+#include "efr32mg1p232f256gm32.h"
+
+#elif defined(EFR32MG1P232F256GM48)
+#include "efr32mg1p232f256gm48.h"
+
+#elif defined(EFR32MG1P232F256IM32)
+#include "efr32mg1p232f256im32.h"
+
+#elif defined(EFR32MG1P232F256IM48)
+#include "efr32mg1p232f256im48.h"
+
+#elif defined(EFR32MG1P233F256GM48)
+#include "efr32mg1p233f256gm48.h"
+
+#elif defined(EFR32MG1P233F256IM48)
+#include "efr32mg1p233f256im48.h"
+
+#elif defined(EFR32MG1P632F256GM32)
+#include "efr32mg1p632f256gm32.h"
+
+#elif defined(EFR32MG1P632F256IM32)
+#include "efr32mg1p632f256im32.h"
+
+#elif defined(EFR32MG1P732F256GM32)
+#include "efr32mg1p732f256gm32.h"
+
+#elif defined(EFR32MG1P732F256IM32)
+#include "efr32mg1p732f256im32.h"
+
 #else
 #error "em_device.h: PART NUMBER undefined"
 #endif
 #endif /* EM_DEVICE_H */
 #ifdef __cplusplus
 }
 #endif
+

cpu/efr32mg1p/vectors.c → cpu/efm32/families/efr32mg1p/vectors.c

@@ -19,7 +19,6 @@
  * @}
  */
 
-#include <stdint.h>
 #include "vectors_cortexm.h"
 
 /* define a local dummy handler as it needs to be in the same compilation unit
@@ -31,7 +30,13 @@ void dummy_handler(void)
 
 /* Silicon Labs specific interrupt vector */
 WEAK_DEFAULT void isr_emu(void);
+WEAK_DEFAULT void isr_frc_pri(void);
 WEAK_DEFAULT void isr_wdog0(void);
+WEAK_DEFAULT void isr_frc(void);
+WEAK_DEFAULT void isr_modem(void);
+WEAK_DEFAULT void isr_rac_seq(void);
+WEAK_DEFAULT void isr_rac_rsm(void);
+WEAK_DEFAULT void isr_bufc(void);
 WEAK_DEFAULT void isr_ldma(void);
 WEAK_DEFAULT void isr_gpio_even(void);
 WEAK_DEFAULT void isr_timer0(void);
@@ -51,14 +56,24 @@ WEAK_DEFAULT void isr_cmu(void);
 WEAK_DEFAULT void isr_msc(void);
 WEAK_DEFAULT void isr_crypto(void);
 WEAK_DEFAULT void isr_letimer0(void);
+WEAK_DEFAULT void isr_agc(void);
+WEAK_DEFAULT void isr_protimer(void);
 WEAK_DEFAULT void isr_rtcc(void);
+WEAK_DEFAULT void isr_synth(void);
 WEAK_DEFAULT void isr_cryotimer(void);
+WEAK_DEFAULT void isr_rfsense(void);
 WEAK_DEFAULT void isr_fpueh(void);
 
 /* interrupt vector table */
 ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [ 0] = isr_emu,                /* EMU */
+    [ 1] = isr_frc_pri,            /* FRC_PRI */
     [ 2] = isr_wdog0,              /* WDOG0 */
+    [ 3] = isr_frc,                /* FRC */
+    [ 4] = isr_modem,              /* MODEM */
+    [ 5] = isr_rac_seq,            /* RAC_SEQ */
+    [ 6] = isr_rac_rsm,            /* RAC_RSM */
+    [ 7] = isr_bufc,               /* BUFC */
     [ 8] = isr_ldma,               /* LDMA */
     [ 9] = isr_gpio_even,          /* GPIO_EVEN */
     [10] = isr_timer0,             /* TIMER0 */
@@ -78,7 +93,11 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [24] = isr_msc,                /* MSC */
     [25] = isr_crypto,             /* CRYPTO */
     [26] = isr_letimer0,           /* LETIMER0 */
+    [27] = isr_agc,                /* AGC */
+    [28] = isr_protimer,           /* PROTIMER */
     [29] = isr_rtcc,               /* RTCC */
+    [30] = isr_synth,              /* SYNTH */
     [31] = isr_cryotimer,          /* CRYOTIMER */
+    [32] = isr_rfsense,            /* RFSENSE */
     [33] = isr_fpueh,              /* FPUEH */
 };

cpu/efr32mg1p/include/cpu_conf.h → cpu/efm32/include/cpu_conf.h

@@ -7,9 +7,9 @@
  */
 
 /**
- * @defgroup    cpu_efr32mg1p Silicon Labs EFR32MG1P
+ * @defgroup    cpu_efm32 Silicon Labs EFM32/EFR32/EZR32
  * @ingroup     cpu
- * @brief       Support for the Silicon Labs EFR32MG1P CPU
+ * @brief       Support for Silicon Labs EFM32/EFR32/EZR32 CPUs
  * @{
  *
  * @file
@@ -31,12 +31,12 @@ extern "C" {
 #endif
 
 /**
- * @brief   ARM Cortex-M4 specific CPU configuration
+ * @brief   ARM Cortex-M specific CPU configuration
  * @{
  */
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
-#define CPU_IRQ_NUMOF                   (FPUEH_IRQn + 1)
-#define CPU_FLASH_BASE                  FLASH_BASE
+#define CPU_IRQ_NUMOF                   (EXT_IRQ_COUNT + 1)
+#define CPU_FLASH_BASE                  (FLASH_BASE)
 /** @} */
 
 /**

cpu/efm32_common/include/periph_cpu.h → cpu/efm32/include/periph_cpu.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_efm32_common
+ * @ingroup     cpu_efm32
  * @{
  *
  * @file

cpu/efm32_common/periph/adc.c → cpu/efm32/periph/adc.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_efm32_common
+ * @ingroup     cpu_efm32
  * @ingroup     drivers_periph_adc
  * @{
  *

cpu/efm32_common/periph/cpuid.c → cpu/efm32/periph/cpuid.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_efm32_common
+ * @ingroup     cpu_efm32
  * @ingroup     drivers_periph_cpuid
  * @{
  *

cpu/efm32_common/periph/dac.c → cpu/efm32/periph/dac.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_efm32_common
+ * @ingroup     cpu_efm32
  * @ingroup     drivers_periph_dac
  * @{
  *