Merge pull request #16813 from jeandudey/doc1

cpu: fix doxygen grouping warnings

cpu/arm7_common/include/thread_arch.h

@@ -16,8 +16,6 @@
  *
  * @author Kaspar Schleiser <kaspar@schleiser.de>
  * @author Heiko Will <heiko.will@fu-berlin.de>
- *
- * @}
  */
 #ifndef THREAD_ARCH_H
 #define THREAD_ARCH_H

cpu/avr8_common/include/thread_arch.h

@@ -15,9 +15,8 @@
  * @brief       Implementation of the kernels thread interface
  *
  * @author      Koen Zandberg <koen@bergzand.net>
- *
- * @}
  */
+
 #ifndef THREAD_ARCH_H
 #define THREAD_ARCH_H
 

cpu/cc2538/include/cc2538.h

@@ -26,9 +26,10 @@ extern "C" {
 /* ************************************************************************** */
 /*   CMSIS DEFINITIONS FOR CC2538 */
 /* ************************************************************************** */
-/** @addtogroup CC2538_cmsis CMSIS Definitions */
-/*@{*/
-
+/**
+ * @addtogroup CC2538_cmsis CMSIS Definitions
+ * @{
+ */
 /** Interrupt Number Definition */
 typedef enum IRQn
 {
@@ -86,7 +87,8 @@ typedef enum IRQn
     PERIPH_COUNT_IRQn     = (MACTIMER_IRQn + 1) /**< Number of peripheral IDs */
 } IRQn_Type;
 
-/** @name Cortex-M3 core interrupt handlers
+/**
+ * @name Cortex-M3 core interrupt handlers
  * @{
  */
 void Reset_Handler(void);        /**< Reset handler */
@@ -113,26 +115,23 @@ void SysTick_Handler(void);      /**< SysTick handler */
 /**
  * @brief CMSIS includes
  */
-
 #include <core_cm3.h>
-
-/*@}*/
+/** @} */
 
 #define IEEE_ADDR_MSWORD            ( *(const uint32_t*)0x00280028 ) /**< Most-significant 32 bits of the IEEE address */
 #define IEEE_ADDR_LSWORD            ( *(const uint32_t*)0x0028002c ) /**< Least-significant 32 bits of the IEEE address */
 
 typedef volatile uint32_t cc2538_reg_t; /**< Least-significant 32 bits of the IEEE address */
 
-/** @addtogroup cpu_specific_Peripheral_memory_map
-  * @{
-  */
-
+/**
+ * @addtogroup cpu_specific_Peripheral_memory_map
+ * @{
+ */
 #define FLASH_BASE                  0x00200000 /**< FLASH base address */
 #define SRAM_BASE                   0x20000000 /**< SRAM base address */
 #define PERIPH_BASE                 0x40000000 /**< Peripheral base address */
 
 #define SRAM_BB_BASE                0x22000000 /**< SRAM base address in the bit-band region */
-
 /** @} */
 
 /** @name CC2538 Special Function Registers
@@ -811,5 +810,4 @@ typedef volatile uint32_t cc2538_reg_t; /**< Least-significant 32 bits of the IE
 #endif
 
 #endif /* CC2538_H */
-
-/*@}*/
+/** @} */

cpu/cc2538/include/cc2538_gptimer.h

@@ -89,5 +89,4 @@ typedef struct {
 #endif
 
 #endif /* CC2538_GPTIMER_H */
-
-/* @} */
+/** @} */

cpu/cc2538/include/cc2538_rf.h

@@ -136,7 +136,7 @@ enum {
     FSM_STATE_TX_CALIBRATION = 32,
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFERRM bits
  */
 enum {
@@ -149,26 +149,26 @@ enum {
     NLOCK      = BIT(0),
 };
 
- /*
-  * @brief RFCORE_XREG_FRMCTRL0 bits
-  */
+/**
+ * @brief RFCORE_XREG_FRMCTRL0 bits
+ */
 enum {
     SET_RXENMASK_ON_TX  = BIT(0),
     IGNORE_TX_UNDERF    = BIT(1),
     PENDING_OR          = BIT(2),
 };
 
- /*
-  * @brief RFCORE_XREG_FRMCTRL1 bits
-  */
+/**
+ * @brief RFCORE_XREG_FRMCTRL1 bits
+ */
 enum {
     ENERGY_SCAN      = BIT(4),
     AUTOACK          = BIT(5),
     AUTOCRC          = BIT(6),
     APPEND_DATA_MODE = BIT(7),
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFIRQM0 / RFCORE_XREG_RFIRQF0 bits
  */
 enum {
@@ -182,7 +182,7 @@ enum {
     RXMASKZERO       = BIT(7),
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFIRQM1 / RFCORE_XREG_RFIRQF1 bits
  */
 enum {
@@ -194,14 +194,18 @@ enum {
     CSP_WAIT         = BIT(5),
 };
 
-/* Values for use with CCTEST_OBSSELx registers: */
+/**
+ * @brief Values for use with CCTEST_OBSSELx registers.
+ */
 enum {
     rfc_obs_sig0 = 0,
     rfc_obs_sig1 = 1,
     rfc_obs_sig2 = 2,
 };
 
-/* Values for RFCORE_XREG_RFC_OBS_CTRLx registers: */
+/**
+ * @brief Values for RFCORE_XREG_RFC_OBS_CTRLx registers.
+ */
 enum {
     constant_value_0 = 0x00, /**< Constant value 0 */
     constant_value_1 = 0x01, /**< Constant value 1*/
@@ -248,8 +252,6 @@ enum {
     disabled         = 0xff, /**< disabled */
 };
 
-/** @} */
-
 /**
  * @name    RF CORE observable signals settings
  */
@@ -278,7 +280,6 @@ enum {
      (CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
 #error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"
 #endif
-/** @} */
 
 /**
  * @brief   Device descriptor for CC2538 transceiver

cpu/cc2538/include/cc2538_rfcore.h

@@ -276,7 +276,4 @@ enum {
 #endif
 
 #endif /* CC2538_RFCORE_H */
-
-/** @} */
-/** @} */
 /** @} */

cpu/cc26x0_cc13x0/include/cc26x0_cc13x0_aux.h

@@ -5,6 +5,7 @@
  * Public License v2.1. See the file LICENSE in the top level directory for more
  * details.
  */
+
 /**
  * @ingroup         cpu_cc26x0_cc13x0_definitions
  * @{
@@ -25,7 +26,7 @@ extern "C" {
 #endif
 
 /**
- * AUX_AIODIO registers
+ * @brief AUX_AIODIO registers
  */
 typedef struct {
     reg32_t GPIODOUT; /**< gpio data out */
@@ -37,9 +38,10 @@ typedef struct {
     reg32_t GPIODIE; /**< gpio data input enable */
 } aux_aiodio_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_AIODIO0_BASE      0x400C1000 /**< AUX_AIODIO0 base address */
 #define AUX_AIODIO1_BASE      0x400C2000 /**< AUX_AIODIO1 base address */
 /** @} */
@@ -48,7 +50,7 @@ typedef struct {
 #define AUX_AIODIO1          ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */
 
 /**
- * AUX_TDC registers
+ * @brief AUX_TDC registers
  */
 typedef struct {
     reg32_t CTL; /**< control */
@@ -63,16 +65,17 @@ typedef struct {
     reg32_t PRECNT; /**< prescaler counter */
 } aux_tdc_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_TDC_BASE      0x400C4000 /**< AUX_TDC base address */
 /** @} */
 
 #define AUX_TDC           ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */
 
 /**
- * AUX_EVCTL registers
+ * @brief AUX_EVCTL registers
  */
 typedef struct {
     reg32_t VECCFG0; /**< vector config 0 */
@@ -94,9 +97,10 @@ typedef struct {
     reg32_t VECFLAGSCLR; /**< vector flags clear */
 } aux_evtcl_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_EVCTL_BASE      0x400C5000 /**< AUX_EVCTL base address */
 /** @} */
 
@@ -142,16 +146,17 @@ typedef struct {
 #define MODCLKEN0_AUX_ADI4_EN       0x00000080  /* enable clock for AUX_ADI4 */
 /** @} */
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_WUC_BASE      0x400C6000 /**< AUX_WUC base address */
 /** @} */
 
 #define AUX_WUC           ((aux_wuc_regs_t *) (AUX_WUC_BASE)) /**< AUX_WUC register bank */
 
 /**
- * AUX_TIMER registers
+ * @brief AUX_TIMER registers
  */
 typedef struct {
     reg32_t T0CFG; /**< timer 0 config */
@@ -162,9 +167,10 @@ typedef struct {
     reg32_t T1CTL; /**< timer 1 control */
 } aux_timer_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_TIMER_BASE      0x400C7000 /**< AUX_WUC base address */
 /** @} */
 
@@ -185,11 +191,12 @@ typedef struct {
     reg32_t AUTOTAKE; /**< sticky request for single semaphore */
 } aux_smph_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_SMPH_BASE               0x400C8000 /**< AUX_WUC base address */
-/* @} */
+/** @} */
 
 #define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */
 
@@ -205,9 +212,10 @@ typedef struct {
     reg32_t ISRCCTL; /**< current source control */
 } aux_anaif_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define AUX_ANAIF_BASE      0x400C9000 /**< AUX_WUC base address */
 /** @} */
 
@@ -230,9 +238,10 @@ typedef struct {
     reg8_t ADCREF1; /**< ADC reference 1 */
 } adi_4_aux_regs_t;
 
-/** @ingroup cpu_specific_peripheral_memory_map
-  * @{
-  */
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
 #define ADI_4_AUX_BASE      0x400CB000 /**< AUX_WUC base address */
 /** @} */
 
@@ -245,4 +254,4 @@ typedef struct {
 #endif
 
 #endif /* CC26X0_CC13X0_AUX_H */
-/** @}*/
+/** @} */