cpu/stm32/periph_pwm: support of complementary timer outputs #19572

gschorcht · 2023-05-10T10:53:04Z

Contribution description

This PR provides the support of complementary timer outputs as PWM channels for advanced timers (TIM1/TIM8).

To use a complementary output of an advanced timer as PWM channel, the output is defined with an offset of 4, i.e. normal outputs are in the range of 0 to 3 (CH1...CH4) and complementary outputs are in the range of 4 to 6 (CH1N...CH3N). If the defined output is less than 4, the normal output is enabled, otherwise the complementary output is enabled.

This change is required to support PWM on boards that have connected the complementary outputs of advanced timers to the PWM connector pins, for example the STM32L496-DISCO board.

Testing procedure

Green CI
Use any STM32 board which supports the periph_pwm feature. tests/periph_pwm should still work.
Change the configuration for this board so that either timer TIM1 or TIM8 and a complementary channel is used for any exposed GPIO. tests/periph_pwm should also work with such a configuration.

Issues/PRs references

riot-ci · 2023-05-10T13:19:51Z

Murdock results

✔️ PASSED

d8cf5a0 cpu/stm32/periph_pwm: add doc for complementary timer channels

Success	Failures	Total	Runtime
6945	0	6945	10m:16s

Artifacts

Documentation preview

benpicco · 2023-05-11T11:00:32Z

@MrKevinWeiss do you have some STM32 boards/PWM tests in your HiL setup?

maribu · 2023-05-15T13:27:40Z

Would you mind to add a bit of documentation (a short 1-3 sentence note would be totally sufficient, IMO). I'm not entirely sure were to add. Maybe the easiest way to find that note would be to add a some "platform specific extensions" to the general PWM doc and add an "STM32" subsection there?

The code looks non-scary. I assume that @gschorcht tested this during development anyway? If so and the doc is added, I'm happy to ACK. Please squash at will.

gschorcht · 2023-05-18T23:08:11Z

@maribu Some doc added for pwm_chan_t.

maribu · 2023-05-19T07:21:17Z

I think you might forgot to push 😅

gschorcht · 2023-05-19T07:23:31Z

I think you might forgot to push sweat_smile

Indeed, see 8b882bf.

maribu · 2023-05-19T08:56:21Z

bors merge

19572: cpu/stm32/periph_pwm: support of complementary timer outputs r=maribu a=gschorcht ### Contribution description This PR provides the support of complementary timer outputs as PWM channels for advanced timers (TIM1/TIM8). To use a complementary output of an advanced timer as PWM channel, the output is defined with an offset of 4, i.e. normal outputs are in the range of 0 to 3 (CH1...CH4) and complementary outputs are in the range of 4 to 6 (CH1N...CH3N). If the defined output is less than 4, the normal output is enabled, otherwise the complementary output is enabled. This change is required to support PWM on boards that have connected the complementary outputs of advanced timers to the PWM connector pins, for example the STM32L496-DISCO board. ### Testing procedure - Green CI - Use any STM32 board which supports the `periph_pwm` feature. `tests/periph_pwm` should still work. - Change the configuration for this board so that either timer TIM1 or TIM8 and a complementary channel is used for any exposed GPIO. `tests/periph_pwm` should also work with such a configuration. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

bors · 2023-05-19T10:58:19Z

Build failed:

Murdock

gschorcht · 2023-05-19T13:03:34Z

I had to push a fixup since not all STM32 MCUs have advanced timer peripherals.

maribu · 2023-05-19T14:34:56Z

please squash :)

To use a complementary output of an advanced timer as PWM channel, the output is defined with an offset of 4, i.e. normal outputs are in the range of 0 to 3 (CH1...CH4) and complementary outputs are in the range of 4 to 6 (CH1N...CH3N). If the defined output is less than 4, the normal output is enabled, otherwise the complementary output is enabled.

gschorcht · 2023-05-20T06:34:59Z

Done

maribu · 2023-05-20T07:27:50Z

bors merge

bors · 2023-05-20T12:39:25Z

Build succeeded!

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gschorcht · 2023-05-21T13:58:49Z

Thanks

18005: pkg/semtech-loramac: model in Kconfig r=aabadie a=aabadie 19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ 19650: drivers/nrf24l01p: model in kconfig r=aabadie a=aabadie 19660: cpu/rpx0xx: Fix kconfig model r=aabadie a=MrKevinWeiss ### Contribution description Broken master due to incorrect model of the periph_pio in kconfig. ### Testing procedure Green murdock (now that the board is added to the list) ### Issues/PRs references Look at the master CI... Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr> Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: MrKevinWeiss <weiss.kevin604@gmail.com>

19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ 19650: drivers/nrf24l01p: model in kconfig r=aabadie a=aabadie 19660: cpu/rpx0xx: Fix kconfig model r=aabadie a=MrKevinWeiss ### Contribution description Broken master due to incorrect model of the periph_pio in kconfig. ### Testing procedure Green murdock (now that the board is added to the list) ### Issues/PRs references Look at the master CI... Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr> Co-authored-by: MrKevinWeiss <weiss.kevin604@gmail.com>

19576: boards: add stm32l496g-disco support r=aabadie a=gschorcht ### Contribution description The PR adds the board definition for the STM2L496G-DISO board. It is the same board that is also shipped with the P-L496G-CELL02 LTE pack for which we already have the board definition `p-l496g-cell02`. However, `stm32l496g-disco` provides a complete configuration of the board and supports the following features in addition to `p-l496g-cell02`: ``` > FEATURES_PROVIDED += periph_adc > FEATURES_PROVIDED += periph_dac > FEATURES_PROVIDED += periph_dma > FEATURES_PROVIDED += periph_pwm > FEATURES_PROVIDED += periph_uart_hw_fc > FEATURES_PROVIDED += arduino ``` In the long term, `p-l496g-cell02` is to be based on the new full `stm32l496g-disco` board definition. The CPT and the LCD display are not yet supported since they are connected to/controlled by the MFX (a STM32L152-based sub-system) and the FMC peripheral. ### Testing procedure All basic tests should work with the new board definition. The following tests were executed and did succeed: - [x] `tests/periph/adc` - [x] `tests/periph/dac` - [x] `tests/periph/i2c` for `I2C_DEV(0)`, `I2C_DEV(1)` is not exposed and not tested - [x] `tests/periph/pwm` - [x] `tests/periph/spi` for `SPI_DEV(0)`, `SPI_DEV(1) connection not soldered and not tested - [x] `tests/periph/timer` for `TIMER_DEV(0)` and `TIMER_DEV(1)` - [x] `tests/periph/uart` for `UART_DEV(0)`, `UART_DEV(1)` and `UART_DEV(2)` - [x] `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` ### Issues/PRs references ~Depends on PR #19571~ ~Depends on PR #19572~ ~Depends on PR #19573~ Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

gschorcht requested review from aabadie, fjmolinas, DipSwitch and vincent-d as code owners May 10, 2023 10:53

github-actions bot added Area: cpu Area: CPU/MCU ports Platform: ARM Platform: This PR/issue effects ARM-based platforms labels May 10, 2023

gschorcht added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels May 10, 2023

gschorcht changed the title ~~cpu/stm32/periph_pwm: allow to use complementary timer channels~~ cpu/stm32/periph_pwm: support of complementary timer outpus May 10, 2023

gschorcht mentioned this pull request May 10, 2023

boards: add stm32l496g-disco support #19576

Merged

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gschorcht changed the title ~~cpu/stm32/periph_pwm: support of complementary timer outpus~~ cpu/stm32/periph_pwm: support of complementary timer outputs May 15, 2023

maribu approved these changes May 19, 2023

View reviewed changes

gschorcht added 2 commits May 19, 2023 16:51

cpu/stm32/periph_pwm: add doc for complementary timer channels

d8cf5a0

gschorcht force-pushed the cpu/stm32/periph/pwm_complementary_timer_outputs branch from a65b680 to d8cf5a0 Compare May 19, 2023 15:49

bors bot merged commit f47003c into RIOT-OS:master May 20, 2023
25 checks passed

benpicco added this to the Release 2023.07 milestone Aug 2, 2023

gschorcht deleted the cpu/stm32/periph/pwm_complementary_timer_outputs branch September 10, 2023 11:21

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cpu/stm32/periph_pwm: support of complementary timer outputs #19572

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gschorcht commented May 10, 2023

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cpu/stm32/periph_pwm: support of complementary timer outputs #19572

cpu/stm32/periph_pwm: support of complementary timer outputs #19572

Conversation

gschorcht commented May 10, 2023

Contribution description

Testing procedure

Issues/PRs references

riot-ci commented May 10, 2023 • edited

Murdock results

Artifacts

benpicco commented May 11, 2023 • edited

maribu commented May 15, 2023

gschorcht commented May 18, 2023

maribu commented May 19, 2023

gschorcht commented May 19, 2023

maribu commented May 19, 2023

bors bot commented May 19, 2023

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riot-ci commented May 10, 2023 •

edited

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edited