Refactor tests periph uart #20281
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Refactor tests periph uart #20281
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Also the LF is display inside the [...]. Now it is more obvious what characters came in on the RX port of the UART. Here is an example: 2024-01-20 20:57:41,368 # send 1 ati 2024-01-20 20:57:41,368 # UART_DEV(1) TX: ati > 2024-01-20 20:57:41,393 # Success: UART_DEV(1) RX: [ati\r\r\n] 2024-01-20 20:57:41,398 # Success: UART_DEV(1) RX: [SARA-N310-00X-00\r\n] 2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [\r\n] 2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [OK\r\n]
keestux
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leandrolanzieri,
aabadie and
MichelRottleuthner
as code owners
keestux
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benpicco
and removed request for
aabadie,
leandrolanzieri and
MichelRottleuthner
benpicco
reviewed
Jan 23, 2024
Teufelchen1
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CI: ready for build
Teufelchen1
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Mar 18, 2024
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Contribution description
The first change is to improve the visibility of incoming CRs (carriage return). They will now be shown as
\r. Also, the LF (that usually comes after a CR) is now shown inside[..], not after the closing].The second change is a re-implementation of PR20128. I hope that @benpicco is not offended by it. I had this change lying around for more than a year, sorry about that. I want to include the change in the current PR because I consider the code in PR20128 too "hackish".
Testing procedure
I've tested the change on a
sodaq-sara-sffboard which has a Ublox SARA N310. For that a few extra steps are needed because the Ublox needs two pins to beON, plus one pin needs to be toggled low for roughly one second. Otherwise the Ublox remains off.After that:
init 1 38400eol_crsend 1 ATHere is an example what you can expect.
Issues/PRs references
None