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cpu/msp430/periph_uart: Fix uart_write() for USCI peripheral [backport 2024.04] #20584

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merged 1 commit into from
Apr 23, 2024
Merged

cpu/msp430/periph_uart: Fix uart_write() for USCI peripheral [backport 2024.04] #20584

merged 1 commit into from
Apr 23, 2024

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maribu
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@maribu maribu commented Apr 16, 2024

Backport of #20572

Contribution description

In TX-only mode the UART was previously release before all bits of the last byte were shifted out. This adds a busy loop waiting while the peripheral is still busy, fixing the issue.

Testing procedure

make BOARD=olimex-msp430-h2618 flash term -C tests/sys/busy_wait now gives:

[...]
2024-04-14 16:05:16,734 # main(): This is RIOT! (Version: 2024.04-devel-652-g3cdc43)
2024-04-14 16:05:16,734 # waiting for 10 µs…
2024-04-14 16:05:16,735 # took 427 µs (diff: 417 µs)
2024-04-14 16:05:16,735 # waiting for 100 µs…
2024-04-14 16:05:16,735 # took 848 µs (diff: 748 µs)
2024-04-14 16:05:16,735 # waiting for 1000 µs…
2024-04-14 16:05:16,735 # took 4508 µs (diff: 3508 µs)
2024-04-14 16:05:16,735 # waiting for 10000 µs…
2024-04-14 16:05:16,736 # took 40651 µs (diff: 30651 µs)
2024-04-14 16:13:23,451 # Exiting Pyterm

With master, there is no output shown because pyterm is waiting for the \n to complete the line. But since \n is incidentally the last char in all strings send (and, therefore, corrupted), it will never show any output.

Issues/PRs references

Regression introduced by #20357

@maribu
cpu/msp430/periph_uart: Fix uart_write() for USCI peripheral
9f3e08e 
In TX-only mode the UART was previously release before all bits of the
last byte were shifted out. This adds a busy loop waiting while the
peripheral is still busy, fixing the issue.

Co-authored-by: benpicco <benpicco@googlemail.com>
(cherry picked from commit f4baa0f)
@maribu maribu added Area: cpu Area: CPU/MCU ports CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: MSP Platform: This PR/issue effects MSP-based platforms Process: release backport Integration Process: The PR is a release backport of a change previously provided to master Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors) labels Apr 16, 2024
@maribu maribu mentioned this pull request Apr 16, 2024
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riot-ci commented Apr 16, 2024

Murdock results

✔️ PASSED

9f3e08e cpu/msp430/periph_uart: Fix uart_write() for USCI peripheral

Success Failures Total Runtime
10044 0 10045 14m:25s

Artifacts

@Teufelchen1 Teufelchen1 added this pull request to the merge queue Apr 23, 2024
Merged via the queue into RIOT-OS:2024.04-branch with commit bd8c054 Apr 23, 2024
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@maribu maribu deleted the backport/2024.04/cpu/msp430/uart_usci branch April 23, 2024 15:32
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maribu commented Apr 23, 2024

Thx :)

@MrKevinWeiss MrKevinWeiss added this to the Release 2024.04 milestone Apr 30, 2024
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@Teufelchen1 Teufelchen1 Teufelchen1 approved these changes

@kaspar030 kaspar030 Awaiting requested review from kaspar030 kaspar030 is a code owner

@gschorcht gschorcht Awaiting requested review from gschorcht gschorcht is a code owner

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Area: cpu Area: CPU/MCU ports CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: MSP Platform: This PR/issue effects MSP-based platforms Process: release backport Integration Process: The PR is a release backport of a change previously provided to master Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors)
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